【作者】 李鹏；

【导师】 罗丰； 张会锁；

【作者基本信息】 西安电子科技大学 ， 工程硕士（专业学位）， 2015， 硕士

【摘要】 现如今,处理器技术的发展日新月异,其对高速大容量存储器性能的要求也越发的严苛。而在各类常用的随机存储器件中,尤以DDR3存储器的使用最为广泛。DDR3存储器具有速率高、容量大、售价低廉等多种优势。由于存储器无法对处理器的访存命令做出直接的应答,且操作起来逻辑十分复杂,对读写时序的要求也尤其严格,因而设计出一款效能良好的存储器控制器将是该领域今后很长一段时间努力的重点。另外,近些年FPGA整体性能的提升也越发的迅猛。新一代的FPGA已经能够提供更多的逻辑资源、更快的运算速度和更丰富的存储器接口解决方案。因此,选用FPGA来辅助进行存储器控制器的设计受到越来越多开发人员的青睐。本文以DDR3高速大容量存储器为研究对象,结合存储器的国内外发展现状,对DDR3存储芯片的特性及使用原理进行了深入细致地分析。最终,设计出一款以Altera公司Stratix Ⅳ系列FPGA为开发平台的DDR3控制器,完成了与新型UniPHY物理接口的集成。之后搭建了相应的测试平台,通过相关软件完成了控制器的仿真测试及FPGA验证工作。测试的结果与预期相符,验证了控制器设计的正确性。具体完成的工作如下:(1)从DDR3存储器的内部结构及工作机理出发,对存储器的读写控制时序进行了详细的分析;(2)系统地规划了DDR3控制器的整体架构,对控制器内部每个子系统的功能、设计思路及实现方式进行了细致的描述;(3)对新型UniPHY物理IP核的内部结构进行了深入的研究,完成了UniPHY物理接口的设计;(4)搭建了软硬件测试平台,采用Modelsim和Quartus Ⅱ 12.1软件对DDR3控制器的数据读写功能进行了系统的测试及验证工作,切实保证了控制器的实际应用价值和良好的稳定性。更多还原

【Abstract】 Nowadays, the development of processor technology changes with each passing day, and the requirements of high speed and large capacity memory are also more stringent. And in all kinds of random memory, especially the use of DDR3 memory is the most widely used. DDR3 memory has many advantages, such as high speed, large capacity, low cost, and so on. Because memory is unable to make a direct response to the processor’s visit to the memory, and the operation of the logic is very complex, the requirements of the read and write timing is also particularly strict, so design a good memory controller will be a long time trying to focus on in the future of this filed. In addition, the overall performance of the FPGA also grew rapidly in recent years. The new generation of FPGA has been able to provide more logic, faster computing speed and more abundant memory interface solutions. Therefore, the use of FPGA to support the design of memory controller is more and more developed by the researchers.In this paper, we choose the high speed and large capacity DDR3 memory as the research object. Based on the development of the high speed and large capacity memory, the characteristics of DDR3 memory chip and the use principle of DDR3 storage chip are analyzed in detail. Finally, a DDR3 controller based on Stratix IV Altera series FPGA is designed, which is integrated with the new UniPHY physical interface. After building the corresponding test platform, we complete the simulation test and the FPGA verification of the controller through the relevant software. As expected, the test results verify the validity of the controller design. The specific work is as follows:(1) Starting from the internal structure and working mechanism of DDR3 memory, the read and write control sequence are analyzed in detail.(2) The overall architecture of the DDR3 controller is systematically planned. The function, design idea and realization method of each subsystem are described in detail.(3) A detailed research of the internal structure of the new UniPHY IP core is carried out, and the design of the UniPHY physical interface is accomplished.(4) The software and hardware test platform is built. The data read and write function of the DDR3 controller is tested and verified by Modelsim and Quartus Ⅱ 12.1 software. The practical application value and the stability of the controller are guaranteed.更多还原