【作者】 王伟；

【导师】 宁宁；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2016， 硕士

【摘要】 超宽带中高精度模数转换器(Ultra-wideband middle-to-high resolution ADC)作为射频前端数据转换器,在无线通信领域扮演着举足轻重的角色。随着工艺尺寸收缩和电源电压降低,器件短沟道效应愈发显著,高性能模拟电路设计愈发困难,作为首选方案的流水线型模数转换器(Pipeline ADC)越来越凸显出其局限性。逐次逼近型模数转换器(SAR ADC)作为新兴方案,其结构简单,功耗低,面积小,易于集成,近几年得到迅速发展,成为时间交织模数转换器(Time-interleaved ADC)的单通道最优解决方案,逐渐在无线通信领域占领一席之地。本论文将高速中高精度SAR ADC列为研究对象,针对各个模块详细分析了用于提高速度的技术措施,并在CMOS 55 nm 1P8M工艺下实现了一款单通道SAR ADC,其分辨率可在10 bit到12 bit之间进行配置,采样频率达到100 MS/s。为保证系统稳定性,该SAR ADC采用纯静态逻辑进行设计,避免动态逻辑中浮空节点受漏电,串扰等影响;为提高转换速度,该SAR ADC采用新型的SAR逻辑电路和极低的DAC电容来优化数字延迟时间和DAC建立时间,新型SAR逻辑电路采用了锁存器型SAR单元,可改善传统触发器的高延迟缺陷,DAC采用非二进制冗余技术,可降低建立时间要求,提高噪声容错能力;为提高系统精度,该SAR ADC被设计成支持两种不同切换模式,以配合特定时间交织校正算法的实施;为提高系统灵活性,该SAR ADC支持分辨率配置功能,以应对不同性能要求场合,避免精度浪费;为提高系统易用性,该SAR ADC使用自适应延迟电路控制SAR环路延迟时间,能够实时跟踪工艺角,温度,电源等变化并作出相应调整;为控制芯片成本,该SAR ADC的“版图设计—后仿真—电路参数优化”过程被多次循环,力求以最小芯片面积实现最优性能。后仿真结果表明,该SAR ADC在100 MS/s采样频率,输入信号频率接近奈奎斯特(Nyquist)频率时,具有10.6 bit的有效位数(ENOB),74.9 dB的无杂散动态范围(SFDR)和65.7 dB的信噪失真比(SNDR),同时在1.2 V供电下消耗15.5 mW的功耗,FoM值为98.5 fJ/conv-step,面积只有50×250μm2。更多还原

【Abstract】 Ultra-wideband medium-to-high resolution analog-to-digital converter, acting as data converter in the RF front-end, plays a crucial role in the field of wireless communications. As the process dismension keeps scaling down and the power supply keeps decreasing, the short-channel effect of devices becomes more significant and the design of high-performance analog circuit suffers from greater difficulties. The pipeline ADC, which was considered to be the best solution, now subjectes to the highperformance op-amp. Successive-approximation-register(SAR) ADC, with the advantages of simple-structure, low-power, area-efficient and digitally-dominant, has developed rapidly in recent years and now serves as the most optimal single channel solution for time-interleaved ADC applied in the field of wireless communications.The paper focuses on the research of high-speed medium-to-high resolution SAR ADC, including the technique details used to decrease the loop delay thus increasing the speed. A 10-12 bits 100 MS/s single channel resolution reconfigurable SAR ADC based on 55 nm 1P8M CMOS process is implemented. To achieve high performance, several techniques are utilized in this paper. To ensure the stability of system, the SAR ADC is designed with static logic, while dynamic logic suffers from the leakage and crosstalk, etc. To improve the conversion speed, the SAR ADC adopts the new SAR logic and DAC with low capacitance aiming at optimizing the digital delay and DAC settling time. A latch-type SAR unit is employed in the new SAR logic, which can improve the shortcomings of traditional high-latency trigger. A non-binary redundant DAC is introduced, which can reduce settling requirement and increase dynamic offset tolerance of each bit decision. To achieve high accuracy of system, the SAR ADC is designed to support two different switching method, enabling the digital calibration algorithm specified for time interleaved ADC. To improve the flexibility of system, the SAR ADC allows resolution-reconfigurable to deal with different requirements and applications, thus avoiding precision waste. To improve the system applicability, the SAR ADC utilizing self-adaptive circuit to control the loop delay, which can track the process, voltage and temperature variation in real-time and adjust itself accordingly. To control the chip cost, the SAR ADC design flow including layout design, post-simulation and circuit optimization is repeated for several time, striving to minimize the chip area while optimal performance is maintained.The post-simulation results show that the SAR ADC sampling a Nyquist frequency sine wave at 100 MS/s achieves a SFDR of 74.9 dB, a SNDR of 65.7 dB and an ENOB of 10.6 bits. The chip core occupies an area of 50×250 μm2 and consumes 15.5 mW with 1.2 V power supply, resulting in a FoM of 98.5 fJ/conv-step.更多还原