【作者】 刘建；

【导师】 李泽宏；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2015， 硕士

【摘要】 旁路二极管(Bypass Diode)主要用于光伏发电中太阳能电池阵列的旁路开关,当太阳出现阴影或其它异常导致光伏电池元胞中出现热点时,电流就会经旁路二极管流过而不会阻断。与传统PN结型和肖特基型旁路二极管相比,新型智能旁路二极管具有更低的正向导通压降、更小的反向漏电流、更低的功耗、更长的寿命以及更稳定的特性,因而迅速成为行业研究热点。新型智能旁路二极管包含一个具有超低正向导通压降的功率VDMOS器件及其栅极自驱动电路。本论文重点研究智能旁路二极管中的VDMOS器件的设计,主要工作如下:在对VDMOS器件的工作原理和电学特性进行了深入的理论分析的基础上,针对智能旁路二极管的应用场景对VDMOS器件的要求,提出一种具有分离栅结构的VDMOS元胞,通过去除常规VDMOS结构JFET区之上的栅电极覆盖,实现极低的栅漏电容。此外,采用JFET区离子注入技术及增加单位面积元胞数目来进一步降低器件导通电阻和栅极电容。结合项目合作方的工艺条件,对超低正向导通压降VDMOS器件的元胞区和终端区进行了结构设计和工艺流程设计。分别利用Tsuprem4和Medici仿真工具对器件结构参数和工艺参数进行了仿真优化,全面系统地研究了外延层、JFET区、Pbody区和N+源区等的物理参数对VDMOS的电学特性的影响,在此基础上获得了优化的元胞和终端的结构参数和工艺参数。最终获得的超低正向导通压降VDMOS器件指标达到:反向耐压40 V、电流能力16 A、阈值电压1-2 V、导通压降48 mV、漏电流10μA、电容1.70 nF。最后,根据优化结果,利用L-Edit软件对VDMOS的器件版图进行了后端设计,完成了整个超低正向导通压降VDMOS器件的设计工作。更多还原

【Abstract】 Bypass Diodes were mainly used in photovoltaic solar array in the bypass switch. When the hotspots being caused by sun’s shadow or other abnormalities occurred in the photovoltaic cell, current will flow through the bypass diodes without being blocked.Comparing to traditional type P-N junction and Schottky bypass diodes, new intelligent bypass diodes have lower forward conduction voltage drop, smaller reverse leakage current, lower power dissipation, longer life and more stable properties and thus becoming research focus. New intelligent bypass diodes contain an ultra-low forward conduction voltage drop power VDMOS device and a gate driving circuit. The main research of this thesis is about the design of VDMOS device of intelligent bypass diodes, and the main works are as follows.After the basic study of theory analysis on the working principle and electric properties, according to the requirements of the scenario of VDMOS device bypass diodes, VDMOS cell with sorting grids structure is presented. By eliminating routine JFET region of VDMOS structure of the gate electrode covering, ultra-low gate-drain capacitance has been achieved. Moreover, using ion implantation technique in JFET region and increaseing the number of cells per unit, we could further reduce on-resistance and gate capacitance of the device.Considering the technological conditions of program partners, we designed the structure and process flow of the cell and terminal area of ultra-low forward conduction voltage drop VDMOS device. We simulated and optimized the device process parameters and structure parameters using Tsuprem4 and Medici and comprehensively and systematically studied the effects of physical parameters of the epitaxial layer, JFET area, pbody area and N+ source region on the electrical properties of VDMOS. On the base, the optimums device process and structure parameters of cell and terminal area have been achieved. To finally obtain the index of ultra low forward voltage drop VDMOS device: reverse voltage is 40 V, current capability is 16 A, the threshold voltage is 1-2 V, conduction voltage drop is 48 mV, the leakage current is 10 μA, the gate capacitor is 1.7 nF.According to the optimum results, we finished the back-end design of the VDMOS device layout using L-Edit, and completed the design of ultra-low forward conduction voltage drop VDMOS device.更多还原