【作者】 邓波；

【导师】 胡剑浩；

【作者基本信息】 电子科技大学 ， 电子与通信工程（专业学位）， 2015， 硕士

【摘要】 Turbo码作为信道编译码方案目前被广泛应用于第三代、第四代以及后续的移动通信应用中,为提高Turbo码译码的性能,可以考虑使用概率计算即使用随机序列来表示数据进而设计Turbo码译码算法和架构。本文以基于概率计算进行设计的全并行Turbo码译码架构为基础进行译码芯片的ASIC设计实现并流片。本文使用Synopsys公司与Mentor公司的相关EDA工具,结合Turbo码译码芯片的ASIC实现对芯片的前端综合、后端物理设计和芯片验证相关技术进行了探索研究,并详细阐述了Turbo码译码芯片前端综合与后端物理实现过程,同时对物理实现完成后的版图进行了相关规则验证与时序后仿真。逻辑综合部分对工艺库与设计约束作了重点分析和说明,并给出了译码芯片经过HDL代码优化后的综合方案和对综合结果的分析;后端物理设计过程中,深入研究了译码芯片的布图规划、电源网络规划、时钟树设计和芯片布线,并简要描述了译码芯片的布局、版图生成以及ECO布线过程;芯片验证部分分别讨论了译码芯片的前端形式验证、后端形式验证、静态时序分析与芯片版图完成后的Antenna/DRC/LVS规则检查,最后对译码芯片进行了时序后仿真以确保芯片在功能和时序上的正确性。在Turbo译码器的ASIC实现过程中,本文结合Synopsys的相关EDA工具对ASIC设计和实现涉及的相关重要知识点进行了总结和分析。此外,还建立了一套完整的基于SMIC130nm工艺的前端综合与物理实现的设计流程和相应Tcl脚本,具体包括逻辑综合、版图实现、版图物理验证、静态时序分析、形式验证和时序后仿真等。这套流程和脚本将为后期其他ASIC芯片设计项目的开发提供参考范例和思路,缩短项目开发时间。最终流片生产的译码芯片相关参数如下:译码芯片基于概率计算,采用MAX-LOG-MAP算法,译码并行度为全并行,译码码长可选,为40到384一共44种可选码长,采用SMIC130nm 1P8M1TM CMOS工艺,规模为百万门级,芯片面积为23.8mm2,译码时钟频率默认工作在100MHz,经仿真测试极限频率可达200MHz。更多还原

【Abstract】 Turbo codes have become an attractive forward error correction scheme and are broadly adopted as channel coding scheme in the third generation, fourth generation and subsequent mobile communication systems. The implementation complexity of traditional high speed turbo decoder is very large, stochastic decoding that is inspired by stochastic computation is an alternative technique for high speed turbo decoder design. The signal data is represented by random sequences in stochastic turbo decoder. In this dissertation, the main research object is the ASIC design implementation and tape out for the fully-parallel stochastic turbo decoder.In this dissertation, the ASIC implementation is performed with the EDA tools from Synopsys and Mentor Graphics. Combined with the ASIC implementation of the fully-parallel stochastic turbo decoder, the dissertation describes and analyzes the related technologies of logic synthesis in the front end, physical design in the back end and chip verification. Meanwhile, the dissertation elaborates the logic synthesis and physical implementation process of the stochastic turbo decoder. In addition, we carry out the layout verifications for the stochastic turbo chip and perform the back-annotated dynamic timing simulation when the chip layout has been achieved. In the logic synthesis, we firstly provide a detailed description to the cell libraries and analyze the main design constraints which can be used to set the target of logic synthesis. Then we propose a synthesis scheme to the optimized stochastic turbo decoder. Finally, static timing analysis is applied to analyze the synthesized information without any timing violations. In the physical design process of the turbo decoder, we research deeply on the floorplanning, power network planning, clock tree synthesis and routing, and a brief description of placement, layout generation and ECO routing. In the chip verification stage, formal verification, static timing analysis and layout verification are discussed. In the end of the dissertation, timing simulation with the layout information is carried out to ensure the correctness of the design.Combined with the ASIC implementation of the design, we summarize some commonly used technologies for each stage of the ASIC flow. Furthermore, the ASIC implementation flow and related Tcl scripts for SMIC130 nm process, including logic synthesis, physical implementation and layout verification, are established. The design flow and scripts can be used as the design reference for the subsequent ASIC projects. The final parameters for the design layout which is fabricated by SMIC are summarized as follows:The fully-parallel stochastic turbo decoder is based on an algorithm which is named MAX-LOG-MAP and the code length is optional, ranging from 44 to 384. The implementation of this design is accomplished based on the SMIC130 nm 1P8M1TM process. This chip is a millions of standard gates scale design, and the layout area of the chip is 23.8mm2. The clock frequency of our design is up to 200 MHz, 100 MHz by default.更多还原