【作者】 李天柱；

【导师】 王向展；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2014， 硕士

【摘要】 随着全球无线通信、雷达等信息系统的飞速发展,高速、高精度、低功耗的高性能ADC显得日益重要。而在各种类型的ADC中,无采保流水线结构的ADC是实现高速、高精度、低功耗ADC的较佳选择。本文基于0.18μm CMOS工艺,对高速高精度流水线ADC的系统架构和关键单元电路进行了深入的研究和分析,并设计了一款16位100 MS/s无采保(SHA-less)的流水线ADC。首先,为了获得功耗较优的系统架构,本文分析了流水线ADC中影响系统性能的一些非理想因素,主要包括电容失配,噪声,运放的有限直流开环增益和有限单位增益带宽等。并在此基础上,结合0.18μm CMOS工艺、关键单元模块的功耗计算和级间电容缩减(Scaling down)技术,确定了功耗比较优的级间精度分配组合的ADC系统架构。其次,针对去掉前端采样保持(S/H)电路后所导致的首级MDAC与Sub-ADC存在不可避免的采样误差,本文采用了一种增益从8降为4的首级3.5位MDAC结构,使首级MDAC具有更宽的冗余位校正范围,提高了首级MDAC对采样误差和比较器失调的容忍,降低了首级MDAC与Sub-ADC之间采样网络的匹配要求。并在此基础上,对第二级MDAC和冗余位校正均做出了相应的调整和修改。另外,针对电容失配对系统造成的误差,本文采用了一种前台校正技术对电容失配所引起的系统的非单调性进行了校正。再次,根据流水线ADC系统的性能指标,基于0.18μm CMOS工艺完成了栅压自举开关、MDAC、比较器等关键单元电路的设计。其中,首级MDAC中的运放采用两级带增益自举和密勒补偿的结构,以满足高增益宽带宽的指标要求。最后,基于0.18μm CMOS工艺完成了各个关键单元电路以及整体流水线ADC版图的实现,并对整个16位100 MS/s无采保流水线ADC进行了后仿验证。后仿结果表明:在采样频率为100 MHz,输入信号频率为10.15625 MHz的条件下,ADC的信号噪声失真比(SNDR)为90.3 dB,无杂散动态范围(SFDR)为103.6 dB,有效位数(ENOB)为14.7位。并且,当输入信号频率增加到47 MHz时,ADC的SNDR和SFDR都分别高于80 dB和85 d B。另外,所设计的ADC在3.3 V的电源电压下功耗为680 mW,版图面积为48 mm2。更多还原

【Abstract】 High performance ADCs of high speed, high precision and low power are becoming increasingly important with the rapid development of global wireless communications, radar and other information systems. The SHA-less pipeline ADC, however, is the better choice to realize the high speed, high precision and low power consumption in the various type of ADCs. The architecture of high speed and high precision pipeline ADC and some key circuits were researched and designed deeply, and a 16-bit 100 MS/s SHA- less pipeline ADC based on 0.18 μm CMOS process was proposed in this thesis.Firstly, in order to get a architecture with lower power consumption, this paper analyses some non- ideal factors of pipeline ADC that affect the system performance, including the capacitor mismatch, noise, the finite dc open- loop gain and finite unity gain bandwidth of op-amp. And then, the systematic precision distribution with lower power consumption of ADC was determined in consideration of 0.18 μm CMOS process, power consumption of key modules and the capacitance reduction(scaling down).Secondly, a technique which has the wider digital correction range of comparator offset and relaxes the timing matching requirement between the Sub-ADC and MDAC sampling networks by reducing the gain of 3.5-bit front-end multiplying digital to analog converter(MDAC) from 8 to 4 is adopted in view of sampling error between the MDAC and the Sub-ADC which caused by removing the dedicated front-end sample-and-hold amplifier(SHA). Meanwhile, the structure of the second stage MDAC and the redundant signed digit(RSD) calibration algorithm were also modified. In addition, based on the error caused by capacitor mismatch, the non-monotonic of system caused by capacitance mismatch was corrected through a foreground correction technique.Thirdly, in terms of requirements of the system, some key modules, like bootstrapped switch, MDAC and comparator, were implemented on 0.18 μm CMOS process. In order to achieve high gain and high bandwidth, the operational amplifier of first stage MCAC was adopted as two-stage gain-boosted and Miller compensated structure.Finally, the layout of some key circuits and entire pipeline ADC were accomplished and post-simulated on 0.18 μm CMOS process. And the post-simulation results show that the ADC sampling a 10.15625 MHz input at 100 MS/s and achieves an SNDR of 90.3 d B, an SFDR of 103.6 d B and an ENOB of 14.7 bit. The ADC has an SNDR of greater than 80 d B and has an SFDR of greater than 85 d B up to 47 MHz input signals. Moreover, The ADC consumes 680 mW from a 3.3 V supply, and the area of layout is 48 mm2.更多还原