【作者】 田永刚；

【导师】 曾志毅；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2015， 硕士

【摘要】 随着通信技术的高速发展,超级计算机、智能终端和多媒体网络等海量数据的快速传输,用户对数据的传输提出了更高的要求。由于串行通信高速率的优点,使其逐渐成为接口的主流技术。IEEE 802.3ae协议定义了一种高速的、灵活的信号传输模式。采用多通道的XAUI(10 Ggigbit Attachment Unit Interface)接口,对信号进行8/10 bit编码,完成10 Gbps数据通信。CDR(Clock and Data Recovery)是串行通信技术领域最关键的电路,也是高速接口速率提升的瓶颈,工作在协议的物理层部分,完成时钟的生成和数据的重定时,对整个通信系统的性能起到了决定性作用。本文基于标准SMIC 0.13μm CMOS工艺,采用自顶向下的设计方法,不断对CDR环路和单元电路进行优化,完成四通道、总有效数据率为10 Gbps的高速C DR电路设计。本课题的主要内容是:1)对PI(Phase Interpolator)电路进行详细的理论分析。把PI的权重因子分为线性的和非线性的分别讨论,找到一种非线性的权重因子可以使PI输出信号的相位有很好的线性度。同时,讨论了PI输入信号的上升时间、输入信号的相位差和输出节点的时间常数三者相互作用对PI线性度的影响。2)本次CDR电路根据XAUI接口标准选择四个通道,每个通道共享PLL电路提供的参考时钟。采用模拟正交相位插值结构的CDR电路,既提高了PI最小相位跳跃精度,又适用于高速电路。电路设计时,先对环路进行适当的改进,加入了差分转单端电路,减小了恢复时钟的峰峰值抖动。然后,根据单元电路设计需求,鉴相器选择半速率的Alexander鉴相器,电荷泵选择全差分结构,并把PI电路的电阻负载改进为对称负载。CDR电路版图的面积为532μm*426μm。单通道输入伪随机序列码的长度为223-1,数据的波特率为3.125 Gbps。仿真结果表明:在SS工艺角下锁定时间为6.2μs,恢复的时钟信号峰峰值抖动为28.8μs,功耗最大在FF的工艺角下为17.2 mW,满足设计要求。更多还原

【Abstract】 With the rapid development of communication technology, the swift transmission of huge amounts of data like super computer, intelligent terminal, and multimedia network, users has put forward higher requirements for the data transmission. Because the serial communication has merits of high speed, it has gradually become the mainstream technology of the interface. IEEE 802.3 ae protocol has defined a high-speed and flexible signal transmission mode. With multi-channel XAUI(10 Ggigbit Attachment Unit Interface), 8/10 bit encoding is made for the signal, 10 Gbps data communication is completed. CDR(C lock and Data Recovery) is the most key circuit in the field of serial communication technology, also the bottleneck of ascension in the rate of high-speed interface. It works in the physical layer of the protocol, completing the generation of clock and retiming of data, which has played a decisive role in the performance of the whole communication system.This thesis based on standard SMIC 0.13 μm CMOS process, using the top-down design method, constantly optimizes the loop of CDR and unit circuit, and completes high-speed CDR circuit design with four channels and the total effective rate of 10 Gbps. The main content of this topic is:1) It has made a theoretical analysis of PI(Phase Interpolator) circuit in detail, discussing the weighting factors of PI respectively by dividing them into linear and nonlinear ones, so as to find a kind of nonlinear weighting factor which can make phase of output signal of PI have extraordinary linearity. At the same time, it has discussed interaction among the risetime of the input signal of PI, the phase difference of the input signal and time constant of output node, and their impact on the PI linearity.2) For the CDR circuit this time, four channels are chosen according to the interface standards of XAUI, each channel sharing reference clock provided by PLL circuit. With CDR circuit of analog quadrature-phase interpolation structure adopted, it has not merely improved the precision of minimum phase jump o f PI, also suitable for high speed circuit. In circuit design, the appropriate improvements have been made to the loop, with differential to single-ended circuit joined, and the jitter of peak-to-peak value of recovered clock has been reduced. Then, accord ing to the design requirements of circuit design in each unit, the halt-speed Alexande phase detector and the differential charge pump are selected in circuit design. The resistors of PI circuit are achieved with PMOS symmetrical load.Layout of CDR circuit covers an area is 532 μm * 426 μm. The length of the pseudo-random bit sequence(PRBS) is 223-1 from a single channel, and the baud rate of data is 3.125 Gbps. The simulation results show that locking time under slow-slow process corner is 6.2 μs; peak-to-peak jitter of restoring clock signal is 28.8 μs; maximum power consumption under the fast- fast process corner is 17.2 mW, this design meets the requirements.更多还原