【作者】 刘建；

【导师】 丁瑞雪；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2014， 硕士

【摘要】 CMOS工艺尺寸的不断减小,给数字电路带来了飞速的发展,数字化时代逐渐到来,作为模拟世界与数字世界桥梁的模数转换器正发挥着无可替代的作用。随着技术的不断发展,满足不同需求的模数转换器相继诞生,其中具有中等转换精度,中等转换速度的逐次逼近型模数转换器(SAR ADC)以其结构简单,功耗低,芯片面积小,研究成本低的特点,从诞生以来,便受到广泛的关注和研究。工艺的改进给模拟电路的设计带来了更大的挑战,由于SAR ADC中不需要线性增益模块,因而较之其他类型的模数转换器更适合工艺的演化路线。近年来SAR ADC凭借其独特的优势,在低功耗应用领域成为新的热点而受到国内外科研团体的广泛研究。本论文设计了一款10位超低功耗SAR ADC。首先对SAR ADC的类型进行了对比分析研究,采用了能耗较低的电荷再分配型结构。在对电容转换网络的结构和不同的电容开关时序下的开关功耗进行研究分析后,提出了一种新型的节能开关时序。该时序巧妙的实现了终端电容的复用,极大的降低了电容阵列的总面积,从而降低了电容阵列的开关功耗。通过建立Matlab模型分析,相对于传统时序,该新型节能开关时序可以将电容阵列的面积和功耗分别优化75%和95.3%。由于电容阵列的功耗在整个系统功耗中所占的比重最大,因而通过采用新时序可以将系统功耗优化到很低的水平。同时,基于新型节能时序的特点,采用了自举开关和基本动态锁存比较器,在满足采样和比较精度的前提下,优化了电路结构,进一步降低了整体功耗,同时抑制了采样开关的非线性和比较器的动态失调。通过分析采样开关电荷注入效应、非线性以及比较器噪声、动态失调等非理想因素,在版图中通过共质心结构,增加dummy管等方法对各个模块做了相应的优化。最后,在完成了版图布局布线后进行了后仿真,其中ADC的内核面积是0.43mm×0.38mm,加上pad后的整体版图面积为1.2mm×1.2mm。在0.6V工作电压、20.8KSPS采样速率下,本论文设计的超低功耗SAR ADC的SNDR为61.8dB,ENOB为9.98位,SFDR为70.48dB,整体功耗仅为88nW,优值FOM为4.2fJ/conversion-step,目前本文设计的SAR ADC的性能在国际领域内具有很高的竞争力。更多还原

【Abstract】 With the decrease of the CMOS process size, the digital circuit has achieved rapid development. The digital age is gradually coming. As the bridge between analog world and the digital world, AD converter is playing an irreplaceable role. With the continuous development of technology in the field of ADC, all kinds of ADCs which meets different needs were born. Successive approximation ADC(SAR ADC) with moderate conversion accuracy, moderate conversion speed has attracted much attention and research from its inception due to the its simple structure, low power, small chip area. Process improvement has brought a bigger challenge to analog circuit design. Because it doesn’t require linear gain blocks, SAR ADC is more suitable for process of the evolution route compared with other types of ADC. In recent years, SAR ADC with its unique advantages has become the new hot spot and has been widely studied in low power applications.A 10 bit ultra-low power successive approximation ADC is designed in the thesis. First, with the comparative study and analysis of the types of the successive approximation ADC, a relatively low-power charge redistribution type structure has been adopted. After doing some research about the structure of the capacitive conversion network and the capacitor switching procedure, a novel energy-efficient capacitor switching procedure is proposed. The scheme realizes the reuse of the terminal capacitance so that the switching energy of the capacitance array decreases because of the smaller capacitor area. Through the analysis of Matlab model, the area and the power consumption of capacitor array have been optimized compared with the conventional capacitor switching procedure, respectively 75% and 95.3%. At the same time, based the features of the novel energy-efficient capacitor switching procedure, bootstrapped switch and the basic dynamic latch comparator are used in the ADC. By analyzing the sampling switch charge injection, nonlinearity, the noise and dynamic offset of comparator, etc., we made corresponding optimization in each module.Finally, we carried on the simulation after layout. The core area is 0.43mm×0.38 mm, and the total area including pad is 1.2mm×1.2mm. At 0.6V supply voltage and 20.8KSPS, the ADC achieves SNDR of 61.8dB, SFDR of 70.48 dB and consumes 88 nW. The FOM of the SAR ADC is 4.2fJ/conversion-step.更多还原