【作者】 王伟；

【导师】 许俊； Leetay Chew；

【作者基本信息】 复旦大学 ， 集成电路工程（专业学位）， 2013， 硕士

【摘要】 当代社会,移动数码设备更新换代日新月异。高速、小面积、低功耗、高性能的模数转换器(Analog-to-Digital Converter-ADC)的发展成为混合信号系统芯片设计的瓶颈,它消耗了大量的人力和开发周期。本文主要研究方向是设计高速、低功耗的中等分辨率的折叠内插结构模数转换器,这种属性的模数转换器在千兆以太网、硬盘驱动、液晶显示驱动和电视机顶盒等领域有广泛的应用。基于应用和设计指标要求,本文采用折叠内插结构作为该类型的模数转换器的设计研究结构。折叠内插结构(Folding and Interpolating)具有高速、芯片面积小、低功耗以及易于兼容先进数字工艺等优点。折叠电路将分辨区间分为粗子量化和细子量化两部分,相比较同等分辨率的快闪型模数转换器而言,减少了模数转换器中比较器的数目,进而降低了电路的复杂性和设计难度,有效降低了电路的功耗和面积；插值电路减少初始参考电路的数目,有效降低前端采样保持电路输出端的输入寄生电容,同时通过插值电路可以实现相邻预放大电路和相邻折叠电路输出端间的失调平均作用,降低信号路径间的偏移而引入的非线性误差。本文设计的电路采用全差分结构,可以有效的提高模数转换器的抗偶数谐波噪声的能力,提高输入电压摆幅；同时采用内插电阻和失调平均电阻共用技术,提高模数转换器的非线性性能,并且进一步减少电路功耗。其次,采用位同步技术,校正了粗细子级量化过程中由于初始参考电压的信号路径失配而带来的误差。本文设计基于联华电子(United Microelectronics Corporation-UMC)标准0.18-μm 1P6M CMOS工艺,设计完成了分辨率为8位,采样频率为500MS/s的折叠内插结构模数转换器。本设计采用HSPICE-D工具进行仿真分析,电路仿真结果表明：在输入信号频率为11MHz时,SFDR为58.8dB, SNDR为48.2dB,ENOB为7.72,功耗为92mW；在输入信号为奈奎斯特频率249MHz时,SFDR为54.9dB,SNDR为47.3dB,ENOB为7.56,功耗为97mW。更多还原

【Abstract】 Nowadays,mobile digital equipment develop so fast.the design of high speed, small size,low power,high performance Analog-to-Digital Converter (ADC) is becoming the bottleneck of mixed-signal SOC design,it consumes a lot of manpower and time.This dissertation mainly study and design a high speed, low power and middle resolution ADC, which can be used widely in Gigabit Ethernet, hard drive, LCD driver, TV set-top boxes and other fields.Based on the design requirements, this study uses folding and interpolating structure as the research direction.Folding and interpolating structure has some advantages such as high speed,small size,low power,ease of digital advanced process compatible.Comparing the same resolution ratio flash ADC,the folding circuit cut the resolution into coarse quantization and fine quantization,which can reduce the number of comparator, and then reduce the complexity of the circuit and design difficulty,also can reduce the circuit area and power effectively.The interpolating circuit can reduce the input capacitance and DNL which generated by the signal paths drift.This whole circuit use fully differential structure,it can improve the ADC noise immunity and enlarges the input voltage effectively.At the same time using interpolation resistance and offset averaging increases nonlinear performance of ADC,and further reduces power consumption..A bit synchronization scheme is proposed to correct the error caused by the signal path mismatch of original refence voltage between the coarse and fine channels.Base on UMC (United Microelectronics Corporation) 0.18-μm 1P6M CMOS process, the dissertation present the design of 8-bits,500MS/s Folding and Interpolating ADC. Using HSPICE-D tool, When the frequency of the input signal is 11MHz, SFDR is 58.8dB,SNDR is 48.2dB, ENOB is 7.72, the power consumption is 92mW. When the input in the Nyquist frequency 249MHz, SFDR is 54.8dB,SNDR is 47.3dB, ENOB is 7.56, the power consumption is 97mW.更多还原