【作者】 王玮；

【导师】 王鹏飞；

【作者基本信息】 复旦大学 ， 微电子与固体电子学， 2014， 硕士

【摘要】 随着器件尺寸的不断缩小以及集成电路中晶体管密度的不断增加,针对新型小尺寸器件的设计和研究也变得更为重要,其中隧穿型晶体管作为低亚阈值摆幅、低功耗的新型器件之一,近年来得到了广泛的关注。本论文通过设计了几种新型的器件结构,使隧穿型晶体管的性能得到优化,并研究了隧穿晶体管在新型半浮栅存储器件中的应用。本文第一部分主要设计并研究了具有U型沟道以及SiGe异质结结构的新型隧穿晶体管。由于隧穿晶体管与普通MOS器件相比,主要缺陷在于其开启电流较低,该部分设计了一种凹陷型的U型沟道增大了TFET的线性隧穿电流,从而达到了增大器件开态总电流的目的。此外,在源极区域使用窄禁带的锗硅材料代替硅材料,可以减小隧穿距离,增大隧穿电流,随后又通过在SiGe源区下方加入delta叠层结构,使得隧穿电流得到了进一步的增大,使得该种结构的性能可以和普通MOS管相比拟。另外,文中还分别研究了U型TFET和平面型TFET尺寸缩小过程对其性能的影响,由于U型沟道可以增大器件的有效沟道长度,与平面型器件相比具有更好的尺寸微缩前景。本文第二部分主要研究了由隧穿晶体管组成的新型半浮栅存储器件,以及一种具有U型沟道的改进型结构。半浮栅存储器件通过在半浮栅MOS中内嵌一个TFET器件,可以在小面积、低功耗的情况下实现存储单元的读写功能,操作电压与普通DRAM相比也可以得到降低。文中还通过将浮栅下方的水平沟道改进为凹陷U型,改善了小尺寸时器件的短沟道效应,使器件尺寸可以得到进一步的缩小。文中还通过仿真对该存储器件操作时的电学原理进行分析,并通过对比U型沟道器件与平面器件随着尺寸减小时电学性能的变化,体现出U型沟道所带来的的优势。文中提出了两种对U型半浮栅器件的优化方法,其一是通过在漏区下方加入高掺杂层来减小保“1”状态保持时的漏电,其二是通过沟道局部注入对浮栅MOS的阈值电压进行调节,从而对“0”“1”态读取电流进行调整。本论文中的工作均采用TCAD软件仿真完成,隧穿模型选择了新的动态非局域隧穿模型,隧穿电流计算更为准确,且模型中的参数均经过了校准。更多还原

【Abstract】 As the continuous scaling down of semiconductor device and the increasing density of transistors integrated into one chip, researches on novel nano-scale devices became more important than ever. Tunneling FET, as one of the most promising future device candidates with small subthreshold swing and low power consumption, has attracted much attention recently. In this paper, We mainly focused on two topics, one of which is the design and optimization of novel tunneling FET, and the other is novel semi-floating gate transistor.The first part of the paper mainly focused on using a u-shape channel and a SiGe heterojunction structure for TFET optimization. When compared to conventional MOSFET, TFET has a relatively low ON current. Therefore, the purpose of this part is to enhance the line tunneling current by using U-shape channel, thus improving the total drain current. Besides, silicon germanium, one of the narrow-band materials, is also used in the source region to shorten the tunneling distant and increase the tunneling current. At last, a highly doped n-type layer is inserted under the source region, further optimizing the ON state performance of TFET. As device dimension is scaled down, the degradation of TFET performance is also investigated by comparing UTFET and planar TFET with different gate length. Because u-shape channel will greatly increase the effective channel length, UTFET has a better scaling performance as compared to the planar one.The second part of the paper mainly focused on investigating the working principle of novel semi-floating gate (SFG) transistor and improving its scalability by using a u-shape channel structure. By integrated TFET into the MOS, a semi-floating gate transistor can achieve excellent read and write operations with small device area and low power consumption. As compared to conventional DRAM, the operation voltage can also be lowered. To improve the electrical performance when the device’s dimension is decreased to nano-scale, a u-shape channel (U-SFGT) could be used to replace the horizontal one. It will inhibit short channel effect effectively. TCAD simulation is used to analyze the working principle of the operation. And the devices with u-shape channel and horizontal channel are also compared under the different channel length. In this way, the merit of U-SFGT is elaborated. We also proposed two methods to optimize U-SFGT, one of which is inserting a highly doped layer to lower the hold "1" leakage current, and the other one is using local channel doping to adjust VT.All the work in this paper is based on TCAD simulation. We used a dynamic non-local band-to-band tunneling model, and the parameters in this model are calibrated.更多还原