【作者】 陈鹏；

【导师】 刘治； 周莉；

【作者基本信息】 山东大学 ， 集成电路工程， 2015， 硕士

【摘要】 LED驱动控制器是LED屏的核心技术,直接决定着LED显示屏的像素密度和显示质量。随着信息技术和高清视频技术的发展,特别是1080P和4K视频出现以后,视频的数据量越来越大,视频的色彩越来越丰富,对LED显示屏的要求越来越高。但是当前市场上的主流LED驱动控制器通信主要依靠串行移位的方式实现,很难实现高速通信,导致刷新速率有限,另外还普遍存在白平衡矫正实现困难的问题。LED驱动控制芯片的通信速率、刷新速率、灰度等级、驱动数量、白平衡矫正等成为了LED芯片发展应用的难题。本课题针对以上分析和实际需要,提出了一种创新型架构,并进行了前后端设计。本文主要讲述以下内容：1)本论文分析了当前LED芯片国内外的发展状况和不足,针对当前LED驱动控制芯片存在的不足,提出了解决这些问题的可行性方案。2)介绍了相关背景技术、具体分析了主流LED显示屏驱动控制芯片架构上的不足,提出了一种新型的架构设计。3)详细介绍了每个模块的架构和实现,并保证有一定的鲁棒性。4)搭建测试平台,从功能测试、鲁棒性测试和FPGA验证三个方面保证设计功能的正确性和可靠性。5)采用Synopsys的标准流程进行本课题的后端设计。本课题的创新之处在于：1)采用双总线设计,实现灵活的地址配置和数据分发；2)通过内嵌SRAM实现伽马矫正数据和白平衡矫正数据的灵活配置；3)采用分布式PWM技术,实现高刷新速率；4)设计初始化模块,实现默认数据的自动配置,简化上电操作。本课题能够弥补现在主流芯片在通信速率、白平衡配置、刷新速率、灰度等级等方面的不足,具有很好的理论研究意义和应用价值。更多还原

【Abstract】 LED driving controller is the core of LED display, which decides the pixel density and display quality. With the development of information and HEVC technology, especially after 1080p and 4K video appears, the data of video increases dramatically, and the color of the video is more and more abundant, which demands higher performance of the LED display. But the communication of main LED driving controller at present is based on serial shifting technology, which is difficult to achieve a higher communication speed and refreshing rate. In addition, white-balance correction is hard to realize. The communication speed, refreshing rate, gray level, driving number and white-balance correction of LED driving controller are key issues in the development of LED chip.The paper aims at the problems above and the practical requirements, proposes a creative architecture, and carries out front-end design and back-end design. The following content will be discussed in the paper:1) The paper analyzes the status and insufficient of LED chip overseas and domestic. Aimed at the insufficient of LED chip, we discuss the feasibility plan.2) Introduce the related technologies, analyze the insufficient of LED chip and raise a new architecture.3) Introduce the architecture and implement each module.4) Create the test platform, and verify the function, robustness and FPGA of the project.5) Carry out back-end design according to the Synopsys design flow.The innovation points are as following:1) Design double bus and realize address configuration and data distribution;2) Realize gamma correction and white-balance correction through SRAM on chip;3) Use distributed PWM technology to raise refresh rate;4) Design initial module and realize auto initialization.The paper can improve communication speed, white-balance configuration, refreshing rate and gray level, and have significance in both research and application.更多还原