动态可重构的基带调制解调器设计

【作者】 周进；

【导师】 王建新；

【作者基本信息】 南京理工大学 ， 通信与信息系统， 2015， 硕士

【摘要】 现场可编程门阵列(Field-Programmable Gate Array, FPGA)凭借着可反复编程、编程速度快等优点受到广泛应用。虽然FPGA的工艺在不断提高,芯片内资源在不断增加,但由于工程中遇到的问题越来越复杂,资源仍是许多项目考虑的第一要素。随着动态部分可重构( Dynamic Partial Reconfigurable, DPR)技术的出现,凭借其节省资源、下载速度快、设计灵活和节省功耗等优点,使得资源问题有了新的解决方案。本文基于软件无线电(Software Defined Radio, SDR)原理,结合动态部分可重构技术设计了一种动态可重构的基带调制解调器。发射端输入信号先经过卷积编码,再选择二相差分相移键控(Differential Binary Phase Shift Keying, DBPSK)、四相差分相移键控(Differential Quaternary Phase Shift Keying, DQPSK)、高斯最小频移键控(Gaussian Minimum Shift Keying, GMSK)中的一种调制方式,然后通过内插改变信号处理速率,最后进行正交调制上变频后输出。接收端对接收信号进行载波同步下变频,再经过抽取降低信号速率,而后定时同步选出最优点进行对应的调制方式解调,最后使用Viterbi算法对卷积编码译码。本文设计的基带调制解调器可实现五种传输速率和DQPSK、DBPSK、GMSK三种调制方式的动态切换。更多还原

【Abstract】 Field-Programmable Gate Array (FPGA) is a group of widely used embedded processers due to its repeated programmable nature and high speed. With the improved the fabrication process, FPGA providers are now able to integrate more computing units on a single chip. However, the tasks feed to the FPGA processers during its engineering application are also becoming more and more computational complicated. Thus, developing an optimized scheme to use the limited computing resources is still the first consideration for the program designer of the FPGA. An emerging technology named Dynamic Partial Reconfigurable (DPR) provides an alternative solution for on-chip resources usage optimization. Among all its benefits, the major advantages of this technology are power and resource saving, flexibility and faster configure.Based on the principle of Software Defined Radio (SDR), this dissertation presents a dynamic baseband modem using the DPR technology. At the transmitting block, the signal first goes through a convolutional coding and then modulated by one of the following modulation scheme:Differential Quaternary Phase Shift Keying (DQPSK), Differential Binary Phase Shift Keying (DBPSK) and Gaussian Minimum Shift Keying (GMSK). After using interpolation to change rate, the signal are up-converted by quadrature modulation and sent to the transmitting end. At the receiving end, we first apply carrier synchronized down-conversion to the input signal and then conduct a decimation to decrease rate of signal. In order to choose the demodulation scheme accordingly, post-timing synchronization method is used to screen out optimized point of the corresponding demodulation scheme. In the end, the data is decoded through Viterbi algorithm from convolutional coding. The baseband modem presented this dissertation has the capability of operating under five different data rates as well as switching dynamically among DQPSK DBPSK and GMSK modulation schemes.更多还原