FPGA结构描述方法的研究

【作者】 胡敏；

【导师】 来金梅；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2012， 硕士

【摘要】 随着现场可编程门阵列FPGA技术的发展,在其应用日益广泛的同时,用户的需求也愈加复杂。目前FPGA的竞争不仅在于设计一款高性能的、可靠的器件,而是提供一个可靠的平台,包括FPGA设计软件、FPGAIP核、FPGA芯片以及相关的服务。FPGA结构描述文件是它们之间沟通的桥梁,因此在FPGA开发过程中,如何提供一套简明的,且能准确描述FPGA硬件信息的结构描述方法显得至关重要。对FPGA结构结构描述方法的研究,学术界已取得了很多成果。但它们要么只是针对简单的开关盒／连接盒模型以及仅包含单一种类互连线的结构,与现代主流商用芯片的结构相去甚远；要么对FPGA布线资源和逻辑块采用暴力描述,使得对应的描述文件太大,不便于人工阅读和软件解析。本文在已有的FPGA结构描述方法的基础上,根据现代主流FPGA是由重复单元在水平和垂直方向复制拼接而成的特点,提出了一种基于层次化重复单元的FPGA结构模型,其中重复单元间的连接关系通过端口序列化模型描述,使得描述文件得到极大的缩小。实验结果表明该方法不仅能描述现代主流FPGA中所有种类的逻辑块和互连线,而且在描述文件大小上至少缩小了63.8%。与此同时,本文搭建了一个FPGA结构描述文件开发平台,该平台能针对已设计完成的FPGA生成相应的结构描述文件。资源遍历测试配置和应用功能电路在芯片FDP3P13和FDP4P13上的通过,表明该平台生成的结构描述文件不仅能完整地、准确地描述FPGA硬件信息,且能配合FPGA软件系统正常地工作。此外,本文针对FPGA结构描述文件的应用做了相关研究,主要包括布线资源图的构建和位流文件生成模块的设计与实现。实验表明该文所设计的位流文件生成模块不仅能完成基本的功能,还能完成循环冗余校验、位流文件加密和压缩等功能。更多还原

【Abstract】 With the development of FPGA technology and widespread of its application, the requirement of the consumers has becoming more complicated. Only a high-performance and robust device could no longer satisfy the various needs of consumers, a reliable platform, including FPGA development suites, FPGA IP cores, FPGA devices and compatible services, is only in need. The hardware description file connects all these parts within the platform, therefore a brief and accurate hardware description method plays a critical role.Many achievements have been made on FPGA hardware description methodology research in academics and industry. Most research models in academics embody only simple CB/SB and single kind of interconnect structure, which is far away behind the modern commercial FPGA architecture. On the other hand, only Xilinx Inc. has made its hardware description methodology research results to the public, while its hardware description file is way huge, which is not convenient for human reading and software parsing.Tiles in FPGA are actually copied and pieced together in FPGA hardware schematics. This paper proposes an FPGA architecture model according to the fact above. This model can be applied to heterogeneous FPGAs and for various interconnecting architectures. Also based on the model, this paper defines a set of complete and detailed grammatical rules to describe the FPGA architecture. Experimental results show that the description method can not only delineate FPGA hardware information but also work correctly with FPGA software system. Compared with VPR6.0the way we describe FPGA chips can be utilized to describe various interconnect structures. The description file is much smaller in size than the Xilinx counterpart (1.1%of the Xilinx counterpart when used to describe Virtex-Ⅱ chip with the gate size of three million gates, thus making manual inspection and software parsing easier.更多还原