信号完整性在高速PCB设计中的应用

【作者】 王祥；

【导师】 来金梅； 谢青；

【作者基本信息】 复旦大学 ， 电子与通信工程（专业学位）， 2013， 硕士

【摘要】 随着集成电路的快速发展,电子产品各方面的性能都得到了空前的提高,如此,高速PCB的设计成了产品性能以及稳定性的关键因素,在高速PCB设计过程当中,叠层设置,PCB中整体器件布局,PCB走线等都会造成信号完整性问题,在本文的主板设计过程中,同样遇到了诸多信号完整性的问题,如时序控制,阻抗不匹配造成了反射,以及串扰和SSN的问题。对于这样的信号完整性问题,本文进行了独特的工程化的设计和控制手段,达到了很好的效果。根据时序等长的要求,每一组的等长我们在实际的PCB走线的过程中做到了15mil的误差范围,误差大概为0.3%到0.5%,这样便很好的保证了在时钟周期内,对于同组数据的并行的处理。对于数据信号线与时钟线的500mil到1500mil的要求,本设计做到了1250mil到1450mil之间的差值,这一点很好的满足了时钟线与信号线在协同工作的过程中时序分配中的数据的建立和保持等时序约束的要求,避免了因时序无法控制而造成的在时钟的控制下信号无法进行正常的控制和处理的情况发生。结果显示,通过我们的时序等长控制的设计方法,完全解决了1333MHz外频CPU不开机的问题。根据阻抗控制的要求,Host Clock、DDR时钟、DDR控制、DDR command DMI等的阻抗被控制在了3%到6%之间,差分对的阻抗被控制在了2%到9%之间,而这完全符合Intel设计向导中的15%和20%的要求,通过这样的流程化控制方法,通过仿真分析发现,因阻抗控制而造成的信号完整性中反射而产生的电压摆幅被限定在了15%左右的过压值范围之内,从而保证了信号的正常传输,本文还通过仿真来进一步确认了通过开关产生的噪声的问题,通过在过孔处添加三个0.1uF的电容从而将因为SSN而产生的噪声降低至最低。如此,我们就彻底解决了在设计中经常出现的因为反射,串扰,同步开关噪声,时序控制不当造成的“挑内存问题”问题,满足了信号完整性以及时序的要求。最后经过测试主板性能稳定,系统工作正常,同时,通过本文的研究工作,对以后的相关设计具有积极的指导意义。更多还原

【Abstract】 With the quickly development of the integrated circuit, the performance of the electronic products in all aspects has been get an unprecedented increasing, so high-speed PCB design has become a key factor in product performance and stability. In high-speed PCB design process, from stackup setting, PCB layout and PCB routing, all of these processes may cause signal integrity issues, in the paper, signal integrity also was involved in the mainboard design process, such as timing controlling reflection from the impedence unmatching, crosstalk and SSN issue. To resolve this issue, special project way and measures are talken based on signal integrity issue, then get a better result.Based on the length matching requirements, every group has been controled within15mil tolerance, it meet the needs for timing exactly. At the same time, signal length and clock length should be within500mils to1500mils, actually we control it within1250mils to1450mils. The result is1333MHz CPU can work correctly. Also host clock, DDR Clock, DDR command and DMI impedence have been controlled within3%to6%, and differential impedence has been controlled within2%to9%. This follows the Intel’s requirements about15%to20%. Based on the reflection and crosstalk analysis, we still find the noise, so we begin to chect the SSN influence, the fact we add three0.1uF capacitor, the noise disappear from the simulation wave. Finally, by the actual test. The motherboard performance is awesome. Meanwhile, all of this work will be helpful with the future design and research.更多还原