【作者】 刘亮；

【导师】 刘晓为；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2014， 硕士

【摘要】 随着微电子技术应用的大量普及，微型化和数字化已经成为加速度计发展的主要趋势。Sigma-delta数字加速度计通过Sigma-delta调制技术可实现较高精度模数转换，从而便于与数字模块进行接口，为此，Sigma-delta加速度计得到广泛研究和应用。然而，当前Sigma-delta加速度计研究依然存在许多瓶颈，其中谐波失真便是影响其性能的一个重要因素。在加速度计许多应用场所，比如地震勘探，对谐波失真性能有着严格的要求。因此，关于加速度计谐波失真的研究对于提升加速度计性能具有重要意义。本文在对加速度计检测原理、Sigma-delta调制原理进行分析的基础上，给出了四阶前馈Sigma-delta加速度计的系统结构，并建立了Simulink理想模型，通过行为级仿真结果表明SNDR为94.6dB，有效位数ENOB为15.42bits。以此为基础，结合非线性系统谐波失真产生机理，对加速度计中机械敏感单元、静电力反馈、积分器、开关等各个模块的非线性进行分析，建立了其非线性模型，分别对其进行了行为级仿真验证；最终建立了系统整体的非线性模型，并对其谐波失真进行了分析，优化调整后系统基底噪声约为-140dB，各次谐波失真约为-110dB。在Simulink行为级设计的基础上，基于0.5μm CMOS工艺条件，完成了四阶Sigma-delta加速度计接口电路晶体管级的设计与仿真，并针对谐波失真对开关、运放等模块的非线性进行优化，电路级仿真结果显示系统基底噪声约为-120dB，各次谐波分量均降低在-100dB以下，这表明系统具有较好的谐波抑制能力。最后，针对电学部分的谐波失真进行了电路级的分析，从而进一步验证谐波失真理论分析结果，并得到一些优化措施。更多还原

【Abstract】 Miniaturization and digitization are becoming the major trends of accelerometerdevelopment. Sigma-delta accelerometer use sigma-delta modulation technique toachieve high-accuracy analog-to-digital conversion, and it is convenient to connect tothe digital circuit modules, so sigma-delta accelerometer is being widely researched andused in these years. However there are many bottleneck problems in the research onsigma-delta accelerometer, the Harmonic Distortion is just one of the most importantfactors to hinder the improvement for the performance of accelerometer. In someapplications, such as seismic prospecting, the HD of accelerometer should be effectivelysuppressed. Therefore the research on HD of accelerometer can make great sense toimprove the performance of accelerometer.In this paper, a structure of forth-order feedforward Sigma-delta accelerometer isproposed based on the analysis for the principle of accelerometer and sigma-deltamodulation, and the ideal model of the system is constructed in Simulink. As the resultsof simulation, the SNDR of system is94.6dB and ENOB is about15.42bits. Then itanalyses for the nonlinearities of some modules in accelerometer, such as sense element,static force feedback module, integrator, switch, etc. The nonlinear models are alsoconstructed in Simulink and verified by simulation. At last the whole nonlinear modelof system is constructed and the HD is analyzed by simulation, as a result the noisefloor comes to-140dB, while the HD is about-110dB.On the basis of system level design in Simulink, the interface circuit ofSigma-delta accelerometer is designed and simulated in transistor level with0.5μmCMOS process, and the linearities of switches and op amps are optimized. Thesimulation indicates that the noise floor of system is about-120dB, while all the HD isreduced to below-100dB, it means that the system can suppress the HD to some extent.Finally the HD of electrical modules is analyzed to verify the theoretical analysis, andthen some optimization method can be obtained.更多还原