【作者】 张伟；

【导师】 姚若河； 钟亮；

【作者基本信息】 华南理工大学 ， 集成电路工程， 2014， 硕士

【摘要】 在高性能视频监控系统中，考虑到传输带宽、外部存储空间的限制以及特定场合图像的无损获取，要求采集端对图像数据能够无损压缩传输。本文基于某公司的视频监控处理平台，采用FPGA实现了JPEG2000图像压缩系统。主要工作如下：1、在实现JPEG2000压缩系统的FPGA结构上，采用模块化的设计方式把整个压缩系统分为预处理模块、分量变换模块、小波变换模块、系数量化模块、Tier1编码器和Tier2编码器模块。2、在小波变换模块:根据实现无损压缩的需求，采用提升5/3离散小波，并且根据小波变换中提升系数的特点，采用映射结构替代通常的乘法运算，减少了关键路径延时，提升了变换速度；根据提升步骤的分裂、预测和更新特点，利用三级流水线实现一维小波变换，优化了硬件资源和速度。3、在编码器模块：Tier1模块包含了位平面编码和算术编码。位平面编码器的设计采用通道并行方案；在算术编码器的实现方式上，采用自适应二进制算术编码和五级流水线方式，提升了编码器的效率。在Tier2编码器模块，根据JPEG2000编码规则，对Tier1编码器输出的压缩数据进行码流组织；根据处理平台的需求，实现20:1的压缩倍数。最后，采用Quartus II和ModelSim进行编译和仿真，并在ALTERA公司的Stratix III的验证版上进行验证，与MATLAB计算结果进行比较，实现了正确的功能。小波变换模块的最高工作频率达到97.64MHZ，FPGA的逻辑资源使用率仅为1%；整个JPEG2000压缩系统的工作频率为89.53MHZ，FPGA逻辑资源使用率为54%，满足实际项目中对1280*720p60Hz图像20:1的压缩要求。更多还原

【Abstract】 In the high performance video monitoring system, taking into account the transmissionbandwidth, external storage space constraint and image lossless acquisition in specificoccasions, end of image data acquisition requirements to transmisslosslessly. In this paper, thethe JPEG2000image compression system are realized by a company`s video processingplatform based on FPGA.the main work of this paper are as follows:First,in the FPGA structure achieving JPEG2000compression system, by adoptingmodular design, the compression system is divided into preprocessing module, componenttransformation module,wavelet transform module,coefficient quantization module, Tier1encoder and Tier2encoder module.Second, in the wavelet transform module,according to the demand of compression, lifting5/3wavelet is adopted and according to the characteristics of wavelet lifting coefficient,in thenumerical calculation,using the mapping structure instead of usual multiplication to To reducethe critical path delay and improve the speed of transform;at the same time, according to thelifting step`s spliting, prediction and update,using three stages pipeline to complete onedimensional transform,finally,utilizing of hardware resources and speed have been optimized.Third,inencoder module:Tier1contains the bit plane coding and arithmetic coding.thechannel parallel is adopted; in arithmetic encoder implementation,adaptive binaryarithmeticcoding and five stages pipeline are used to improve the efficiency of the encoder.in Tier2encoder module, according to the JPEG2000encoding rules, organizing the compressed dataof Tier1encoder output; according to the requirement of the platform, achieving20:1compression.Finally, we use Quartus IIand ModelSim to compile and simulate and downloadcodes toALTERA company’s StratixIII version for authentication verification and the results werecompared with MATLAB andachieves the correct function. In the wavelet transform module,the maximum operating frequencyis97.64MHZ,FPGA logic resource usage is only1%.Entire JPEG2000image compression system operating frequency is89.53MHZ, FPGA logicresources utilization rate is54%,meeting the real project`s requirements for1280*720p60Hz20:1lossless image compression.更多还原