【作者】 李龙；

【导师】 朱樟明；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2014， 硕士

【摘要】 高速高精度CMOS D/A转换器是现代移动通信领域、数字信号处理、图像处理以及无线通信网络等电路系统中的关键模块。同时，D/A转换器作为软件无线电应用中重要IP核，也发挥着越来越重要的作用。就现阶段高速高精度发展领域来看，应用于通信和无线设备中的D/A转换器需要有至少500MHz的速度和大于14位的系统精度。这意味着D/A转换器在高速高精度领域，必然成为各个相关研究单位和企业的热点和关键技术。本文基于中芯国际(SMIC)0.18μm1P6M标准CMOS工艺，实现了一种16位GHz采样的分段式高动态性能电流舵D/A转换器，其供电采用3.3V/1.8V双供电电压，6-10分段结构，其中高6位为温度计编码，低10位则采用二进制编码。本文所设计的D/A转换器流片测试，采样时钟频率最高可达为1GHz。开关电路采用四相开关电路，有效减小电路在高频应用下的杂散噪声的影响；在开关电路前应用低交叉点对控制信号进行处理并驱动开关控制信号的驱动电路，可以抑制由于始终馈通所导致的输出毛刺现象的发生；通过偏置技术为电流源阵列提供精准的电流值；电流源采用高速设计中常用的共源共栅结构用以提高电流源的输出阻抗，同时减小时钟馈通效应对输出结果的影响。本文设计的16位1GHz D/A转换器采用差分输出结构，满量程输出电流20mA，通过外接电阻50Ω的电阻转换成输出电压并且做双端转单端处理，进一步减小偶次谐波对电路系统带来的影响。论文采用Spectre对所设计的16位D/A转换器进行了仿真，系统的建立时间可以达到1.1ns，系统积分非线性误差为±1.1LSB，微分非线性误差为±0.6LSB。并基于Agilent频谱分析仪对设计实现的16位1GHz D/A转换器进行测试，在采样时钟为1GHz下，输入信号为10MHz的正弦信号，其无杂散动态范围(SFDR)可以达到79.93dB。芯片总功耗为358.66mW，芯片核心面积约为1.65×1.25mm2，可以满足现代无线通信以及软件无线电领域的要求。更多还原

【Abstract】 The high speed high accuracy CMOS D/A converter is the key module of the modernmobile communication, DSP, image processing and wireless network. Work as theimportant IP core of software radio, D/A converter seem more and more important.Generally, the performance of the D/A converter in the mobile and wireless device is atleast500MHz rate and14-bit accurate. This means that the development of high speedhigh accuracy D/A converter must become the hot point and key tech among relativeinstitute and company.This thesis is based on SMIC0.18μm1P6M standard CMOS technology achieve a16-bit GHz sample rate segmented high dynamic character current steering D/Aconverter whose supply voltage is3.3/1.8. The D/A converter is6-10segmentedstructure, in which the6MSB are thermometer coding and the10LSB are binarycoding. The most high sample rate could reach to1GHz from test after tape-out. Theswitch circuit using quad-switch, which could reduce the impact of the high frequencynoise effect; a low cross control signal is used to drive the switch circuit, and couldsuppress the glitch phenomenon caused by switch clock feed-through; obtain precisecurrent value from the reference current array; current source using the cascadestructure to increase the output impedance and decrease the effect of clock feed-through.The16-bit1GS/s D/A converter using differential output, full scale output current is20mA, according to a50Ω resistance transfer from current to voltage and double-end tosingle-end, which could reduce the even harmonic power in the system frequency band.The thesis is based on Spectre simulate the designed16-bit D/A converter. Thesetting time is1.1ns, the INL is±1.1LSB and DNL is±0.6LSB. Furthermore, based onAgilent Spectrum Analyzer, we test the designed16-bit1GHz D/A converter chip.Under the1GHz sample clock and input signal is10MHz sinusoidal signal, the SFDRof the DAC could reach to79.93dB. The power of the whole chip is358.66mW and thearea of the chip is about1.65×1.25mm2, which have already satisfy the requirement ofthe wireless communication and software radio.更多还原