【作者】 王敏；

【导师】 柯导明；

【作者基本信息】 安徽大学 ， 微电子学与固体电子学， 2014， 硕士

【摘要】 MOSFET非本征部分产生寄生电容会影响器件的性能,如何降低寄生电容的大小,一直是国内外学者的研究热点。集成电路的集成度一直遵循摩尔定律,器件特征尺寸的不断缩小要求MOSFET的栅氧化层厚度越来越薄,因为薄栅氧化层厚度能改善器件的特性并能有效抑制短沟道效应。但是超薄栅氧化层厚度会产生栅极泄漏电流,并且寄生电容并不随器件尺寸的减小而成比例减小,因此必须用低漏电流且物理厚度大的高K栅材料代替二氧化硅作为栅介质。以往求解寄生电容的模型,用保角变换的方法和数值法只能求解普通栅MOSFET的寄生电容,将结果直接应用到高K栅MOSFET中,必须要添加修正因子才能与仿真结果一致。半解析法是将解析法和数值法结合的一种计算方法,既能像解析法得到准确的表达式,也能像数值法灵活处理复杂的边界条件。本文使用的半解析法是解析法中的分离变量法和数值法中的矩形等效源法的结合。本文首先用矩形等效源法简化MOSFET的物理模型,得到不含任何近似的栅源电势定解问题。然后采用分离变量法求解电势,用特征函数展开法求解电势表达式中的未知系数。再根据高斯定理得到电荷,继而求出寄生电容和本征电容的表达式。最后是对模型的验证和讨论,研究结果显示,减小源区长度和栅电极厚度可以减小寄生电容,栅氧化层厚底的减小会使寄生电容增加,寄生电容随着栅介电常数的增加而减小,寄生电容几乎不随沟道长度的变化而变化。因此,器件设计者可以根据计算结果选择最合适的器件参数,设计出满足需要的最小寄生电容的MOS器件。本文提出的半解析法求解MOSFET寄生电容的过程,没有使用任何近似,得到的是含有器件参数的电容解析表达式,因此可直接用于器件设计和电路模拟程序中。本模型求解寄生电容时精度高、运算量小,不仅能求解普通栅MOSFET的寄生电容,对高K栅MOSFET同样适用。更多还原

【Abstract】 The extrinsic of MOSFET cause parasitic capacitance will affect the performance of the device, how to reduce the parasitic capacitance has been a hot topic to domestic and foreign scholars. The integration of integrated circuit always followed Moore’s Law and the MOS device size continue to shrink, so the gate oxide thickness of MOSFET requires to be much thinner, the reason is that the thin gate oxide thickness can improve the characteristics of MOSFET and can suppress the short-channel effects effectively. But the ultra-thin gate oxide thickness will cause a gate leakage current, besides the parasitic capacitance does not decrease with the decrease in proportion to the device size, so the high k dielectric which has low leakage current and thick physical thickness substitute SiO2as the gate material is needed. The previous parasitic capacitance model, with the conformal mapping method can only solve the parasitic capacitance of common MOSFET, the results used to the high k gate MOSFET directly require correction factor to correct the results. Semi-analytical method is the combination of analytical method and numerical method, it can obtain accurate expressions like analytical method, and also could be deal with complex boundary conditions flexibility like the numerical methods. The semi-analytical method of this paper is a combination of separation of variables method and rectangular equivalent source method.In this paper, we simplified the physical model of MOSFET by rectangular equivalent source method to obtain the gate-to-source definite solution of potential without any approximation. Then using the separation of variables method to solve the potential, and solving the unknown coefficients in the expressions of potential by the characteristic function expansion method. According to the Gauss’s law, the expressions of parasitic capacitances and the intrinsic capacitance can be obtained. Finally, the model validation and discussion is studied. The results show that the parasitic capacitances decrease with a decrease in the source length and the gate electrode thickness; as the gate oxide thickness decreases, the parasitic capacitances increase; the parasitic capacitances decrease as the gate dielectric constant increases; while as the channel length decrease, the parasitic capacitances do not change. Therefore, according to the results, the device designer can select the most appropriate parameters to design a MOSFET with the minimum parasitic capacitances. This paper presents the semi-analytical method to study parasitic capacitances of MOSFET without any approximation, the analytical expressions of capacitances with device parameters are obtained, so it can be used in the device design and circuit simulation program directly. The model has high precision, small calculation; it also can be used for both the common gate MOSFET and high-k gate MOSFET.更多还原