【作者】 彭军；

【导师】 黎福海；

【作者基本信息】 湖南大学 ， 电子科学与技术， 2013， 硕士

【摘要】 随着信息技术的飞速发展，人们对数据存储容量和速度需求越来越高。传统计算机系统采用的机械硬盘由于其较大的I/O访问延迟、功耗高、抗震性差等问题成为限制存储系统性能的瓶颈，已经逐渐不能满足未来应用的需求。基于NAND Flash的固态存储系统由于具有读写速度快、非易失性、抗震性、功耗低等优势，经逐步发展和多次技术变革，逐渐显露出其巨大的优势，受到了国内外学者和工业界人士的普遍重视，未来或将替代传统硬盘。但如何充分提高闪存的实际访问带宽，降低I/O访问延迟，并且发挥多路闪存并行访问优势，是固态存储系统设计中需要重点考虑的问题。本文设计并实现了一种基于NAND Flash的多路并行固态存储系统。整体设计以FPGA为开发平台，采用SOPC技术，在FPGA内搭建多通道固态存储控制器架构，通过外接多片Intel公司的大容量NAND Flash芯片，构建了多路并行存储系统。该系统采用高速SATA接口连接到主机，内置多个独立工作的NANDFlash控制器，采用并行总线拓宽技术，大大提高了NAND Flash的访问带宽。在多通道并行存储架构的基础上，本文对多通道架构下的FTL进行了研究。首先，针对通道架构的特点，提出了一种基于超级块和μ树的混合地址映射策略，该策略一方面使FTL能充分利用多通道架构中的多种并行性，另外一方面有效的减少了地址映射占用的内存。其次，结合新型NAND Flash在数据搬运方面的优势，对传统的基于贪婪算法的垃圾回收机制进行了优化，提出了一种新的垃圾回收块权值定义，有效的缩短了垃圾回收的时间，提高了垃圾回收的效率。然后，对传统的动态均衡损耗算法进行了优化，提出了一种基于冷热数据的均衡损耗策略，解决了传统算法磨损不均匀的缺陷。最后完成系统的模块测试与整体测试，介绍了测试平台、测试方法以及测试流程，给出了测试数据和结果分析，得出了验证结论。测试结果表明，本文所设计的多路并行固态存储系统能正常稳定工作，具有良好的并行性。更多还原

【Abstract】 With the high development of the Imformation technology, the demand for datastorage capacity and speed is growing. The mechanical HDD adopted by traditionalcomputer storage system has become the bottlenecks of storage system and can’tmeet the demand of the future appications because of its huge I/O access latency,high power cusumption and poor shock resistance. At the same time, afterprogressive development of a number of technical change, the NAND Flash-basedsoild state storage system which has rapid read and write speed, non-volatile, goodshock resistance and low power consumption gradually revealings its great advantageand attracts the attention of the domestic and foreign scholars and the industry. Itmay replace the traditional HDD in the future. However, the issue of increasing theactual Flash access bandwidth, decreasing the I/O latency and exploting theparallisms between multi-channels should be considered in the design of solid statestorage system.This paper designs and implements a multi-ways storage systems based onNAND Flash. Through using FPGA as the developemt platform and exploting theSOPC technology, the design constructs a solid state storage controller architecturein the FPGA. By exploting serval high capacity Intel NAND Flash chips, it constructsa multi-ways parallel solid state storage system. The system is connected to the hostby SATA and uses serval independent NAND Flash controllers to increase the accessbandwidth of NAND Flash by explot parallel bus broaden technology. This paperdoes a research for the FTL of the multi-channel architecture. Firstly, it proposes ahybrid address translation scheme which is based on super block and μ-tree. On theone hand, this address translation scheme can explot the multi parallisms of themulti-channel architecture. On the other hand, it reduces the RAM memoryconsumption of address translation. Secondly, in order to explot the advantage ofCopy-back command in the advanced NAND Flash and shorten the garbage collectiontime, the FTL optimizes the traditional greedy algorithm and proposes a newdefinition of dirty block. Thirdly, the FTL proposes a wear-leveling algorithm basedhot and cold data indentification to optimize the disadvantage of the traditionaldynamic garbage collection algorithm. At the end of this paper, the module andsystem is tested and validated. It presents the test platform, method and processes, then gets the test results and draws the validated conclusions. The tese results showsthat this parallel solid state storage system can word stablely and has good prallellsim.更多还原