【作者】 李健；

【导师】 李斌桥；

【作者基本信息】 天津大学 ， 微电子学与固体电子学， 2012， 硕士

【摘要】 时间延迟积分(Time Delay Integration，TDI)是指对移动中的同一物体进行多次曝光并将曝光结果进行累加，等效增加像素对物体的曝光时间，减少像元间响应不均匀和固定图像噪声的影响，从而提高图像传感器的信噪比和灵敏度，使其在低照度条件下仍能获得高分辨率的图像，广泛应用于航空遥感、医学成像等领域。本文通过系统建模验证128级TDI CMOS图像传感器数字域累加方案，并对时序控制电路进行研究。本文介绍了TDI CMOS图像传感器的工作原理，并分析了全局曝光与滚筒式曝光这两种曝光方式各自的特点；结合相关双采样与过采样滚筒式曝光，在降低读出噪声的同时实现信号的同步采集；分析了传感器扫描速度与像素尺寸的关系，研究了积分采样过程和速度失配对于系统调制传输函数的影响；针对模拟积分电路容易出现电压饱和的情况，采用先量化、后累加的数字域累加方法，充分利用模数转换器的量化范围。采用Verilog-A和Verilog HDL分别对TDI CMOS图像传感器中的像素、模数转换器及累加电路进行建模后，配合时序控制电路进行仿真，验证了数字域累加方案的可行性。根据数字域TDI算法设计并优化电路结构，每列共用加法器以降低芯片面积，通过仿真观察512列负载对时序控制信号线的影响；在像素阵列上按照红、绿、蓝三色为一组的排列方式放置彩色滤光片，并对电路结构及时序控制电路做出修改，使TDI CMOS图像传感器输出RGB模式真彩色图像。本文通过模数混合仿真验证电路的功能，并完成时序控制电路的逻辑综合、布局布线、静态时序分析及物理验证，采用GSMC0.18m工艺进行流片。系统主时钟为40M，累加电路为1~129级可调，渡越时间34s、258s可调，单列累加电路版图面积为30m6023m，时序控制电路版图面积为116m5200m。更多还原

【Abstract】 Time delay integration (TDI) refers to that the moving objects are exposedrepeatedly and exposure results are accumulated. The total exposure time isequivalently increased and the effect of response nonuniformity and fixed patternnoise is reduced. Signal to noise ratio and sensitivity of the image sensor are increased,so that it is able to achieve high resolution images in low illumination conditions. TDItechnology is widely used in the aviation remote sensing, medical imaging and otherfields. In this thesis,128-stage digital accumulation scheme in TDI CMOS imagesensor was verified through system modeling and the timing control circuit wasresearched.This thesis introduced the principle of TDI CMOS image sensor and analyzedthe characteristics of global shutter and rolling shutter. Combined correlated doublesampling with oversample rolling shutter, readout noise was reduced and signal wasacquired synchronously. The relationship between sensor scanning speed and pixelsize was analyzed, and effect on system modulation transfer function caused byintegration and sampling, and speed mismatch. Compared with the condition ofvoltage saturation in analog integrating circuit, the method of accumulation in digitaldomain after quantization made full use of ADC quantization range. After modelingfor pixels, analog-to-digital converter and accumulation circuit in TDI CMOS imagesensor with Verilog-A and Verilog HDL, the feasibility of digital accumulationscheme was verified with timing control circuit simulation. Structure of the cirsuitswas designed and optimized according to TDI algorithm in digital domain and chiparea was decreased by sharing the adder for each column. The influence of loads in512columns on bus of timing control was observed through simulation. Color filterswere placed on the pixel arrays where red, green and blue ones were a group, and thecircuit constructure and the timing control modules were modified for TDI CMOSimage sensors to get true color images in RGB pattern.In this thesis the function of the circuits was verified by mixed signal simulation.Logic synthesis, placement and routing, static timing analysis and physicalverification for timing control circuits were completed, and the chip was taped out inthe process of GSMC0.18m. The system clock is40M, and the stage ofaccumulation circuit is adjustable from1to129. The line time is also adjustable for34m or258s. Layout area of the accumulation circuit for each column is30m6023m, and that for timing control circuit is116m5200m.更多还原