【作者】 高军；

【导师】 喻明艳；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2012， 硕士

【摘要】 乱序超标量处理器中广泛存在的集总式结构已严重限制微处理器性能的提升。EDGE(Explicit Data Graph Execution)作为应对微处理器性能提升瓶颈的模型之一，从结构模型中摒弃了超标量中能耗大不易扩展的集总式结构。在分布式EDGE结构中，指令映射到多个分片上同时执行。分片之间操作数传递需要延时从而导致性能下降。指令映射算法通过仔细权衡程序的并行度和分片间通信延时来试图消除分片后带来的性能损失。TRIPS微处理器采用关键资源拓扑结构不对称分布和静态指令映射算法(SPDI, Static Placement Dynamic Issue)。这会导致ET(Execute Tile)上较大的负载不均衡和操作数网络通信热点，从而引起IPC下降。本文在M5-EDGE模拟器中实现与TRIPS类似的EDGE结构，以此来研究指令动态Deep映射算法。在缺乏编译器调度下，采用循环映射方式的Deep算法在发射宽度为1和2时IPC分别为SPDI的85%和98.3%。针对RT(Register Tile)和DT(Data-cache Tile)的拓扑位置，对Deep映射进行三种优化：依照ET编号顺序、“之”字形顺序和计算甚块全局通信跳步数之和来优先选择ET。在发射宽度为1时三种优化与基本的Deep算法相比平均跳步分别减少2.63%、2.18%和4.70%，而IPC分别提升1.07%、1.21%和2.11%。这说明在Deep映射下优化指令间通信跳步数能显著提高IPC。在Deep映射算法中，90%以上的操作数通过操作数旁路来传递，大大减少操作数网络的负载。在bypass宽度为2倍发射宽度时，本地的操作数传递延时几乎下降为0。增加本地bypass宽度，能有效的减少操作数传递的延时。将RT按编号分配到ET上，基本Deep映射算法的IPC提升1.77%。针对DT位置进行优化，优先选择靠近DT的ET和计算甚块通信跳数之和选择ET。这两种优化比基本Deep映射IPC分别提升1.17%和1.89%。将RT和DT平铺到ET中形成4x4的拓扑结构。在发射宽度为1和2时该结构中Deep映射的IPC分别为SPDI的97.18%和113.42%。计算跳步数选择ET，这一比值为97.32%和114.06%。微结构变化导致拓扑距离变小或者Deep映射算法优化通信跳步数时，能显著提高系统IPC。更多还原

【Abstract】 Monolithic structure commonly used in out-of-order superscalar processorshas severly limited performance improvement of microprocessor. EDGE, as one ofthe models used to cope with the bottleneck in the performance improvement ofmicroprocessor, aborts the monolithic power hungry and unscalable structure in itsarchitecture model. In distributed EDGE architecture, instructions are mapped toexecute in several tiles at the same time. The operand communication among tilesneeds delay and leads performance degradation. The instruction mapping algorithmtries to mitigate the performance loss due to operands communication delay bycarefully balancing the communication delay among tiles and degree of parallelism.In TRIPS microprocessor, critical resources scatter asymmetric in topologyand static instruction mapping algorithm is used. This will lead unbalance in load atETs and hot spot in operand communication network, which will result inperformance degradation.In this paper, an EDGE architecture like TRIPS is implemented to studyinstruction dynamic Deep mapping algorithm in the M5-EDGE simulator. Resultshow that Deep mapping with round-robin fashion at choosing ET with issue width1and2, the performance is85%and98.3%compared with SPDI, without compiler’sschedule and optmization. When take the RT/DTs’ topology location intoconsideration, choosing ET using numbering sequence, zigzag sequence andcalculating global communication hops of a hyperblock to choose a tile asoptimizations. Average hops are decreased by2.63%、2.18%and4.70%respectively, and IPC are improved by1.07%、1.21%and2.11%respectively，compared with the base Deep mapping algorithm at the issue width1.Optimizations which decrease communication hops of instructions can improve IPCnotably.Over90%operands are delivered by local bypass path in Deep mapping,which largely alleviate load of OPN. Simulation shows that when the bypass widthis2fold of the issue width, the delay of local operands bypass is nearly0. Byincreasing width of local bypass path, latency of operand delivery can be decreasedeffectively. When put RTs into ETs according to register number, IPC gained in base Deepmapping algorithm is improved by1.77%. Taking DTs’ location into considerationas optimizations, ETs close to DTs are preferentially selected and calculatehyperblock’s communication hops to select a proper ET. These optimizationsimprove IPC by1.17%and1.89%compared to base Deep algorithm. When RTsand DTs are distributed into ETs, a4x4grid topology is obtained. IPC gained byDeep mapping algorithm is97.18%and113.42%with issue width1and2,compared SPDI. A simple optimization above Deep, these comparisons is97.32%and114.06%. IPC will be improved notably when topology hops decrease becauseof micro-architecture changes or optimizations over Deep mapping algorithm.更多还原