【作者】 张亮；

【导师】 李广军； 周刚；

【作者基本信息】 电子科技大学 ， 电子与通信工程（专业学位）， 2012， 硕士

【摘要】 随着光通信系统向大容量、远距离、高速率的方向迅猛发展,光通信接入技术不断提高,传输速率也在快速的变化,10G速率的光模块也逐渐占进入了大规模商业化应用。本文所研制的基于FPGA的10Gpbs误码仪集合了误码测试功能和误码模拟功能为一体,同时针对1OG XFP光模块接口和多种电接口的特殊要求,开发了一种低成本,而且实用的误码模块。相比于传统光通信误码仪有以下特点：第一,PRBS码型从PRBS3至PRBS31连续可调,以适用于不同协议条件下的测试；第二,误码测试仪的码流速率是可调的,范围从9.953Gbps-11.37Gbps。第三,同时提供XFP插座接口和SMA接口,即可以做XFP光模块误码测试仪又可以作为普通误码测试仪使用。第四,支持多种环回模式,可以对通从而实现长距离测试,输入输出双向均可取反。第五,允许手动插入单个误码或等间距插入误码,从而具有随机分布特性。本文第二章简要介绍了误码检测仪的检测原理；第三章作为设计总体方案的介绍,其中还对硬件设计进行了阐述；第四章至第六章为误码测试模块的详细设计及仿真阐述,包括误码产生与比对模块、SFI4.1协议接口模块、控制模块三部分；本文第七章针对设计进行了测试,并给出了相应的测试结果。本文详细介绍了基于FPGA的10Gbps误码测试仪的设计方案,利用Altium Designer完成了原理图和PCB的设计与实现；通过Verilog HDL语言在Xilinx Virtex5完成了误码测试模块的设计与实现,包括以下几个方而：1、FPGA与MCU之间的EPP通信；2、根据用户设置,产生对应长度和对应速率’下的PRBS序列,并进行误码个数及累计时间的统计。3、模拟信道功能,手动插入误码。4、误码测试模块内部两种环回模式(外部三种)。误码测试仪在PRBS31码型下进行不同速率的电口眼图测试,1000点测试结果为：RMSJ<2.1ps, PPJ<14ps,眼图Margin>24%,达到了设计要求,性能良好。更多还原

【Abstract】 With the rapid development of optical communication system towards large-capacity, long-distance and high-speed, and the continuous improvement of optical communication access technology, the transfer rate change quickly, also optical module of10G rate, has been put into large-scale commercial application, have come into being. In this paper, a FPGA-based10G BERT is introduced as a kind of transceiver, which combines bit-error test function with error analog function. Meanwhile, according to the special requirements of the10G XFP optical module interface and the multiple-electrical interfaces, the author developed a low cost and practical error module.Compared with traditional one, this optical communication BERT has the following characteristics. Firstly, PRBS code line can be continuously adjusted from PRBS3to PRBS31to be applied in testing under different conditions. Secondly, the BERT stream rate is also adjustable, ranging from9.953Gbps to11.37Gbps. Thirdly, the BERT provides both XFP socket interface and SMA interface that can be used as XFP optical module BER tester and ordinary BER tester. Fourthly, it supports a variety of loop-back mode, by passing through, one can achieve long-distance test, and the input and output two-way can be negated. Fifthly, it allows manual insert, not only for single error, but also for equidistant insertion error. As a result, is has random distribution characteristic.Chapter Two has a brief introduction of the principle of BERT. As the discussion of the overall design scheme, Chapter Three elaborates the design of hardware. The content of Chapter Four to Six are the specific design as well as the simulation of bit error tested module, which include the bit error generation and contrast module, the network-interface module based on the SFI4.1protocal, and the control module. The result and data of measurement was supplied in Chapter Seven.This paper introduces a FPGA-based lOGbps Bit Error Tester plan in detail, With Altium Designer, the author completed schematic and PCB design, and completed the error test modules design in Xilinx Virtex5by Verilog HDL language. It includes the following aspects:1) EPP communication between FPGA and MCU.2) According to user settings, it brings in a PRBS sequence with a corresponding length and rate, and counts out the number of the errors and time.3) The analog channel function, and manual error insertion.4) Two types of loop-back modes in the error test module (three types outside).The BERT has been tested in the electrical eye diagram under the PRBS31pattern with different rate, and the results at1000test point show as follows:RMSJ<2.1ps PPJ<14ps, Eye diagram margin>24%. So it has reached the design requirements with good performance.更多还原