【作者】 汪洋；

【导师】 耿相铭；

【作者基本信息】 上海交通大学 ， 电子与通信工程（专业学位）， 2013， 硕士

【摘要】 随着半导体行业和集成电路行业的不断发展，市场开始追求体积更小、功耗更低、功能更强的产品。一种以嵌入式系统为核心，将软件和硬件集成到一起，并追求系统最大包容的集成芯片越来越流行，这就是片上系统（System On Chip，SOC）。随着片上系统复杂度的不断增加，芯片验证的复杂度也成指数倍的增长，芯片验证的压力越来越大。软硬件协同验证技术作为芯片验证的关键技术，起着越来越重要的作用。在软件硬件协同验证中，一个好的软硬件协同验证平台能够在芯片流片之前准确的反映软件和硬件设计中出现的问题，以提高流片成功的几率。如何设计出快速准确的软硬件协同验证平台，已经成了一个相当重要的问题。本文针对软硬件协同验证平台中的速度和可见性问题，系统的介绍了最近流行的电子系统级（Electronic System Level，ESL）设计技术及其虚拟平台软件Soc Designer，介绍了硬件加速技术及其设计平台EVE板，将这两种技术和传统的软硬件协同验证技术（HDL仿真技术和FPGA板级验证技术）进行了比较，说明了这两种技术的优缺点。在此基础上，提出了一种将Soc Designer平台和EVE平台相结合的联合验证平台的架构设计方案，该方案综合了ESL技术和硬件加速技术的优点。然后，以导航SOC为例，根据Soc Designer平台和EVE平台之间的通信方式的不同，选择对基于共享内存的通信方式和基于socket的通信方式的联合验证平台进行了实现，给出了两个平台之间的通信机制和同步策略，并验证了整个联合验证平台设计的正确性。最后，将联合验证平台和纯Soc Designer设计的系统进行了仿真效率的比较，在认真分析了比较的结果后，设计了三个仿真速度的优化方案：联合系统工作方式的优化、Soc Designer处理器的优化和EVE硬件加速器的优化。并对优化后的系统进行了仿真效率的测试，证明了优化后的联合验证平台确实能有效的提高仿真速度，并在仿真的逼真度、可见性、速度上取得了平衡。更多还原

【Abstract】 With the continuous development of semiconductor industry andintegrated circuit industry, the market began to pursue a smaller size、lowpower consumption and more powerful products. The System on chip(SOC)which combines CPU s, memories and peripheral units in a chip hasbecome more and more popular. However, with the rapid growth of theSOC complexity, SOC verification complexity’s growth is exponential. Sothe pressure of SOC verification is vary large. As the key technology ofSOC verification, software and hardware (SW/HW) co-verificationtechnology plays a more and more important role. In SW/HWco-verification technology,the verification platform is very important. Agood SW/HW co-verification platform can find the design problems ofhardware and software before taping out. How to design an accurate andrapid verification platform has been a big problem.This paper introduces the ESL technology and its virtual designplatform Soc Designer, introduces hardware acceleration technology andits design tool,EVE board. Compares them with the traditional verificationplatform: RTL platform, FPGA platform,introduces their advantages anddisadvantages. Then puts forward a joint architecture which combinesthese two technology. And uses navigation SOC as an example, introducesits concrete realization(both socket version and shared memories version).Gives two platform’s communication mechanism and synchronizationscheme. Verifies the correctness of the whole system. Last,compared itwith pure Soc Designer system,gets the simulation efficiency of bothsystems, gives and verifies three Optimization schemes which is used to accelerate its simulation speed. The result proves that the joint architectureactually gets a balance in simulation speed and accuracy.更多还原