【作者】 李勇；

【导师】 周炎涛；

【作者基本信息】 湖南大学 ， 电子科学与技术， 2012， 硕士

【摘要】 21世纪随着计算机和通信技术日新月异的发展,信息安全也就变得越来越重要了。而密码学是解决信息安全问题的非常有效的技术。随机数在现代密码技术中有着非常重要的地位,例如：数字签名、密钥管理和几乎所有的密码协议和算法等都要用到随机数。所以现代密码学的安全性的一个重要的来源就是产生机密数据的随机数的随机性。而产生随机数的装置也就是随机数发生器,现在广泛使用的随机数发生器是伪随机数发生器。因为它产生随机数的原理是采用相应的数学算法来递推得到“随机数”,而不是利用物理过程中的各种随机噪声。伪随机数发生器大多有结构简单、占用硬件资源少、速度快等特点,但是其随机性差。而且一旦“种子”被人盗取,那么它产生的随机序列就确定了,所以它不能被使用在对安全要求很高的系统中,如：银行系统、安全芯片等。真随机数发生器之所以能产生不可预测的真随机数,是因为其利用了物理过程中的各种随机噪声,如：热噪声、闪烁噪声等,而这些噪声都是不可预测的。本论文的主要内容就是在芯片上设计一个满足信息安全要求的真随机数发生器子模块。本真随机数发生器子模块设计的主要思路是：利用慢速抖动振荡器采样高速振荡器来产生随机序列,然后用异或链来消除随机序列的偏置,得到“0”和“1”均匀分布的随机序列。最后随机序列经过串并转换模块,存储到异步FIFO中。为了防止攻击者使用探针探测获取芯片中的敏感信息,提高芯片的安全级别,本随机数发生器还设计了防拆电路。当有探针探测芯片,接触到防拆网络时,随机数发生器就会被断电,并清除FIFO中随机数和停止工作。为降低芯片的总体功耗,随机数发生器中使用了门控时钟技术,只有当FIFO未满的时候,振荡器才会给随机数发生器的数字部分提供时钟。本设计分为模拟和数字部分,模拟部分主要是振荡器,数字部分包括：异或链、混频电路和异步FIFO;自动布局布线工具使用的是Snopsys的ICCompiler。布局布线得到版图,再使用Mentor公司的Calibre对版图进行LVS和DRC验证。验证成功后,完成整个真随机数发生器的设计。本设计采用的HJTC0.18um CMOS工艺来实现。更多还原

【Abstract】 The21st century with the rapid development of computer and communication technology, information security becomes increasingly important. Cryptography is a very effective technique to solve the problem of information security. An important source of security of modern cryptography is to generate the randomness of the random number of confidential data. Now widely used pseudo-random number generator, it produces the principle of random numbers using mathematical algorithms to get "random number". Pseudo-random number generator is characterized by simple structure, less occupied by hardware resources, speed, but its randomness. Once the "seed" was stolen, then its output sequence is not random. so it can not be used in the system of high security requirements such as:banking system, security chip.True Random Number Generator is able to generate true random number that can not be predicted, because the use of physical processes in a variety of random noise, such as:thermal noise, flicker noise. The main goal of paper is to design a module to meet the safety requirements on the IC.The main idea of the true random number generator sub-module design: the slow jitter oscillator sampling high-speed oscillator to generate the random sequence, and then use the XOR chain to eliminate the bias of the sequence to get the random sequence of "0" and "1" Uniform distribution. At last random number stored in the FIFO. In order to prevent the attacker uses probes to detect access to sensitive information in the chip and improve the security level of the chip, anti-tamper circuit is designed in this random number generator. When the probe exposed to anti-tamper network, the random number generator will be powered off and clear the random numbers stroed in FIFO. To reduce the overall power consumption clock gating is used in the design.The design is divided into analog and digital sections, The main part of analog is oscillator, and the remaining are the digital. The EDA tool of Automatic placement and routing we used is sysnopsys’s IC Compiler. And the GDSII generated by IC compiler is run LVS and DRC verification by Mentor Calibre. After successful verification, the entire design of the true Random Number Generator finished. This design uses the HJTC0.18um CMOS process to achieve.更多还原