【作者】 袁鹏；

【导师】 王友仁；

【作者基本信息】 南京航空航天大学 ， 测试计量技术及仪器， 2012， 硕士

【摘要】 随着半导体制造工艺的快速发展，数字电子系统的复杂度大幅增加，在生命周期内发生故障的可能性也随之增大。因此，在一些对可靠性有严格要求的应用领域，例如航空航天，数字电子系统的容错设计显得尤为重要。可重构电路的结构特性为设计高可靠的数字电子系统提供了更为灵活的方法，而现有的可重构电路容错设计方法存在冗余资源利用率低，容错算法复杂以及依赖外部处理器等问题，因此，研究可自主容错的新型可重构电路具有重要意义。本文主要对自主容错可重构电路的结构设计及其容错方法进行了研究，主要研究工作如下：（1）针对传统可重构电路容错方法依赖外部控制、难以在线实现以及冗余资源利用率低等问题，本文设计了一种可实现阵列在线自主容错的分层可重构阵列结构，该阵列分为组织层、细胞层和模块层，在此结构基础上，提出了一种分层容错机制，能够对故障进行精确定位，并以较小的硬件开销完成修复。可重构阵列中的功能细胞设计采用了热备份的思想，保证了容错的在线实现。容错控制方法借鉴了免疫机制，设计了一种用于测试和修复控制的管理细胞，该细胞负责对功能细胞进行测试，并根据故障测试结果选择合适的容错机制。实验表明，分层可重构阵列结构的容错机制灵活、冗余资源利用率高，容错过程不影响阵列的正常工作。（2）为了简化测试流程，降低时间开销，以及提高细胞自身容错能力，设计了一种可在线自测试与自修复的细胞结构，实现了细胞在线自主容错。给出了一种细胞内部逻辑模块的循环自测试方法，并提出了一种针对查找表多位故障的自修复方法。实验表明，细胞容错过程在线进行，自测试与自修复的时间开销较小，细胞容错能力得到提升。（3）将应用实例电路在本文设计的可重构电路上实现了功能映射，应用Modelsim软件进行了仿真分析。采用Xilinx公司的型号为XC2S200-5PQG208C的FPGA芯片为核心，研制开发了可重构电路验证实验板，将设计的可重构电路下载到实验板中进行了测试，验证了设计的可行性和正确性。更多还原

【Abstract】 With the rapid development of semiconductor manufacturing technology, the complexity ofdigital electronic systems greatly increases, and the failure probability also increases during thelifetime of digital electronic systems. Therefore, in some application fields which have strict requestof high reliability, such as aerospace, the fault-tolerant design of digital electronic systems isespecially important. The structure characteristics of reconfigurable circuit provides more flexibleapproaches for the design of high reliable digital electronic systems, however, the existingfault-tolerance design of reconfigurable circuit has low redundancy resources utilization, complexfault-tolerant algorithm, and usually depends on external processor. Therefore, the research ofautonomous fault-tolerant reconfigurable circuit has great importance.This paper mainly researches the structure design and the fault-tolerance approach ofautonomous fault-tolerant reconfigurable circuit, the main research work is as follows:(1) The fault-tolerance approaches of traditional reconfigurable circuit usually depend onexternal control, and most approaches are difficult to realize online, and the redundancy resourcesutilization is low. To solve these problems, this paper designs a hierarchical reconfigurable array,which can realize online autonomous fault-tolerance at array-level. This array is divided intoorganization layer, cell layer and module layer, base on this structure, a hierarchical fault-tolerancemechanism is proposed. Using this mechanism, the array is able to locate fault accurately, and use lesshardware to complete repair. In this reconfigurable array, the function cell design uses the principle ofhot back-up to ensure realization of online fault-tolerance. The fault tolerant control method borrowsthe idea from immune mechanism, and a new kind of cell, named management cell, is designed toperform the testing and repair control. The management cells can test function cell, and chooseappropriate fault-tolerant mechanism by fault diagnosis. The experiment indicates that, thefault-tolerant mechanism of this hierarchical reconfigurable array is flexible, the redundancy resourceutilization rate is relatively high, and the fault-tolerant process does not affect the normal work ofarray.(2) In order to simplify the testing process, reduce the time cost, and improve fault-toleranceability of cells, this paper designs a novel cell with online self-test and self-repair ability, and realizeonline autonomous fault-tolerance at cell level. A cycle self-test method is given to test the logicblocks inside the cells, and a new self-repair method is proposed to deal with the multiple faults of lookup table. The experiment indicates that, the fault-tolerant process is carried out online, the timecost of self-test and self-repair process is relatively low, and the cell’s fault-tolerance ability ispromoted.(3) The application circuit instances are realized function mapping on the reconfigurable circuit,and Modelsim software is used to carry out simulation analysis. Using Xilinx XC2S200-5PQG208CFPGA as core, we design and develop reconfigurable circuit verification board. Then thereconfigurable circuit is downloaded to verification board for testing, and the experiments verify thefeasibility and correctness of the design.更多还原