【作者】 张希；

【导师】 罗嵘；

【作者基本信息】 清华大学 ， 电子科学与技术， 2011， 硕士

【摘要】 随着集成电路的发展，互连线受到芯片规模增大、工艺尺寸下降和工作频率提升等多种因素的影响，出现了性能和可靠性降低的问题，并已成为阻碍集成电路进一步发展的主要障碍。近年来，碳纳米管技术和三维集成技术作为解决这些问题的热门技术得到了工业界和学术界的广泛关注，并有望成为下一代集成电路的主流技术，使摩尔定律得以延续。本文针对基于碳纳米管的三维芯片中布局布线方法进行研究，通过仿真来进一步验证基于碳纳米管的互连结构与传统铜互连结构相比的显著优势。此外，由于FPGA芯片存在的可编程、单元成本低等优势，本文着重研究了三维FPGA结构，并提出了基于碳纳米管的布线规则，为未来三维FPGA芯片的设计和制造提供了有力的实验依据和方法支持。为了解决由接触电阻引起的碳纳米管短导线的性能弱势，本文提出了碳纳米管导线与铜导线的分割算法，其特点在于可以综合利用两种导线的优势，尽可能减小互连线上的延时。此外，本文对三维芯片中碳纳米管通孔的信号传递性能和热传导性能进行了衡量，为设计者提供了更全面的参考信息。针对三维FPGA芯片，本文提出了基于碳纳米管导线的线长分布规则，遵循这一规则可以有效提高芯片的性能，为设计者提供设计方法依据。通过多种三维FPGA芯片的结构分析和优化重组，利用本文提出的优化布线方法，本文最终提出了一种基于碳纳米管的新型三维FPGA结构。该结构具有小尺寸、高性能和低功耗等特征，可以为未来三维芯片的设计和制造提供一定的结构基础和参考依据。本文还对碳纳米管作为芯片封装管脚进行了不同频率下的仿真，证实了碳纳米管管脚可以显著降低电源/地线反弹噪声，改善信号的完整性。更多还原

【Abstract】 With the development of integrated circuits, interconnects suffer fromperformance and reliability problems due to large scale, small size and highoperating frequency. In recent years, carbon nanotubes and three-dimensionalintegration, as solutions to these problems, have been the most populartechnology in industry and academic research, which is expected to becomethe mainstream in future ICs. This paper is focused on placement and routingfor3D ICs based on CNTs. This work can test and verify the advantages ofCNTs compared to copper. Also, consider that Field Programmable GateArrays have many advantages such as programmability and low unit cost, thispaper explores FPGAs in particular. The CNT-based interconnect rulesproposed in this paper will provide strong experimental basis to the designand manufacturing of future FPGAs.In order to solve the performance weak of CNT short wires caused bycontact resistance, this paper presents a partition algorithm which can use theadvantages of both CNT wires and copper wires and minimize the path delay.Besides, the performance and thermal conductance of CNT-basedthrough silicon via in3D ICs are evaluated to provide designers with morecomprehensive reference information.In this paper, the wire distribution rule is proposed, which can enhancethe performance of CNT-based FPGAs. Also, a novel high performance andlow power3D FPGA architecture based on CNTs is proposed, which canprovide strong support of method to future3D FPGA designers.According to simulation results, this paper proves CNTs can be used aspackage pins which can significantly reduce power/ground bouncing noise.更多还原