【作者】 陈飞；

【导师】 沙金；

【作者基本信息】 南京大学 ， 集成电路工程， 2012， 硕士

【摘要】 随着当今高端数字网络设备系统越来越快的速度以及越来越高的复杂度,更高性能、更大容量SRAM的需求成为了制约设计的重要因素。传统的静态存储器方案无法适应其要求。同样是静态存储体系结构,速度更快、吞吐量更大的静态存储器——QDR型SRAM成为了当今的主流选择,其带宽是传统静态存储器的4倍。QDR提供了相互独立的读/写数据通路,从而满足了诸如ATM交换机和网络路由器的性能需求。每个存储器时钟周期内,QDR的读／写两个通路均使用DDR(双倍数据速率)传输发送两个数据字,一个在时钟上升沿时发送,而另一个在时钟下降沿时发送。因此,在每个时钟周期内,QDR会传输四个与总线宽度相等的数据(即两个读数据和两个写数据),这就是QDR(四倍数据速率)的由来。QDR SRAM的存储器架构在数据访问时,不需要变换读/写周期,因此大幅度提高了存储器的数据吞吐量,并且还可以对同一地址进行同时访问。本文介绍一种QDRII与QDRII+SRAM控制器设计,其具有很高的灵活性,可得到广泛运用。本文首先对QDRII与QDRII+SRAM结构进行了研究,主要了解其芯片管脚及读/写状态的转移。深入研究QDRII与QDRII+SRAM控制器的整体构架、读写状态转移以及接口,分析延迟。本文中使用Avalon-MM接口作为主机和控制器之间的接口,其交换式接口具有更高的带宽,支持对多个从属端的进行数据传输。然后对UniPHY的结构和功能做了详尽的分析,包括时钟与重置系统、地址与指令通路、Avalon端口与AFI端口、读/写操作的状态转移。UniPHY是Altera公司推出的一个可自行设计参数的宏功能IP,只支持字对齐操作,其优点是延迟较少,在多存储器控制器系统中支持PLI/DLL共享,并能兼容Altera公司的另一种为DDR系列开发的ALTMEMPHY IP。本文基于Altera公司的UniPHY模块对QDRII与QDRII+SRAM控制器进行设计,包括Avalon从端口设计、与UniPHY IP连接的AFI端口设计,以及读写状态机的设计。结合Altera公司的UniPHY模块对本文所设计的QDRII与QDRII+SRAM控制器进行仿真平台的搭建,编写测试激励,并在Model sim软件中进行仿真,观察波形结果,然后对其进行数据分析,从而进一步理解控制器的结构和功能。更多还原

【Abstract】 With the development of the high-end digital network equipment, which is faster and faster and has more and more complexity, the need of the SRAM, which has better performance and larger capacitor, has become the important factor to restricting the design. The old SRAM cannot fit the need, while as the same architecture of SRAM, Q.DR SRAM has become the choice, which is faster and has bigger throughput capacity and it’s bandwidth is4times as the old one.QDR provides independent read and write interface, which meets the need of the equipment such as ATM switchers and routers. In every cycle, the two path use DDR (double data rate) transfer the data, one in the positive edge of the clock, the other in the negetive edge. Therefore, there are four data word on the bus in one cycle (two for read, two for write). That is what we call the quarter data rate (QDR). QDR don’t need to change the cycle for read or write, so the throughput is improved a lot, and read and write can operate in the same clock cycle. In this paper, the QDRII and QDRII+SRAM controller will be introducted, which is more flexibile, and can be widely applied to the processors and external devices for better communication.The architecture of QDRII and QDRII+SRAM is studied in this paper, including the pins and how to read and write. More studied will made in QDRII and QDRII+SRAM, including the hole architecture, the read/write transfer and the interfaces, and then discuss the latency, In this paper, Avalon-MM Interface will be used as the interface between the controller and the host, which has more bandwidth and can support the multiple slavers. And then the structure of the UniPHY will be shown, which includes the clock and reset system, address and command path, the Avalon interface and the AFI interface, the status transition of the read or write operation. UniPHY is an IP of Altera, which has less latency, share the PLL/DLL in multiple controllers system, and can be compatible with ALTMEMPHY IP. In this paper, QDRII and QDRII+SRAM controller with UniPHY will be designed, including the design of Avalon-MM slave interface, AFI interface and the read/write FSM. Then, build the platform for the design and write the driver, simulate this QDRII and QDRII+SRAM controller with UniPHY in the Modelsim-Altera, watch the waveform and analysis the outputs, in order to have further understanding of the controller.更多还原