【作者】 徐辉；

【导师】 施国勇；

【作者基本信息】 上海交通大学 ， 电路与系统， 2012， 硕士

【摘要】 由于模拟集成电路设计的复杂性与经验性,其辅助设计软件的自动化程度一直不高,只能为设计者提供少量的反馈信息,导致设计者往往要通过反复的电路仿真才能确定电路参数,拉长了电路的设计周期。为此,本文提出了一种针对模拟集成电路的多层次符号化分析仿真器,旨在通过符号化的仿真信息进一步指导电路的设计,提高模拟电路设计的效率。该仿真器结合了基于拓扑网络的符号化分析及基于行列式的符号化分析这两种方法,为每个子电路构建符号化的导纳矩阵,并符号化地求解顶层的电路系统矩阵,从而实现了电路层面的共享,进一步提升了仿真器的处理大型模拟电路的能力。本文的第一章首先介绍课题背景,包括课题的由来,符号化仿真的现状;第二章详细介绍了多层次符号化分析的理论算法基础;第三章给出了符号化仿真器的具体实现,包括仿真器的架构,主要数据结构与算法的实现;第四章给出了仿真器性能的测试结果及一些应用实例;第五章总结全文,并展望了基于该仿真器的进一步改进与应用。更多还原

【Abstract】 Highly automatic electronic design tools for analog circuit design are scare due to its great complexity and experience-based design flow. Repeated simulation iterations are usually involved for analog circuit designers to reach the design specification. On the other hand, the advent of SOC design results in an ever enlarging gap between designers’productivity and a shorter time to market requirement. To address this problem, a hierarchical symbolic analysis method is proposed in this paper, aiming to increase the design efficiency with the inherited merits of symbolic analysis.The proposed method combined a topological symbolic approach with its algebraic counterpart on two hierarchies. Circuit regularity was fully utilized. Symbolic stamps of sub-circuits with different structure were constructed and assembled to the top circuit matrix, then solved by an algebraic symbolic solver. The simulator’s capability of handling large scale analog circuit was improved greatly due to the hierarchical scheme and a compact data structure.The thesis is organized as follows. A brief introduction is listed in Chapter 1. Algorithm and theory of hierarchical symbolic analysis are described in Chapter 2. Chapter 3 talks about the implementation details of the simulator. Chapter 4 presents the experimental results. Chapter 5 summarizes the paper.更多还原