【作者】 孙伟；

【导师】 黄大庆；

【作者基本信息】 南京航空航天大学 ， 通信与信息系统， 2010， 硕士

【摘要】 随着时代的发展,数字图像分割提取系统的结构日益复杂,对图像处理速度的要求越来越高。传统的数字图像分割提取系统多运用通用微处理器芯片,有些数字图像处理对时间要求非常苛刻,以至于用高速的通用微处理器芯片也无法在规定的时间内完成必要的运算。因此,必须为这样的运算设计一个专用的高速硬件逻辑电路,在高速FPGA器件上实现或制成高速专用集成电路。本课题介绍了图像分割及其相关技术的理论基础与其对应的系统电路组成,提出了数字图像分割提取系统中的图像边缘检测、距离变换和模板匹配三大步的解决方案。由于实验条件和时间限制,只实现了该系统前两大步骤的详细设计过程,并且针对图像边缘检测电路像素值数据的并行输入问题,本文提出增加了数据“串并”转换电路来解决,同时给出了该电路的详细设计过程和性能分析。因此,本课题的顶层系统由数据“串并”转换电路、图像边缘检测电路和距离变换电路三大模块组成。在图像边缘检测电路模型设计中,本文充分地分析了前人对该电路设计结构的优点和缺点,并针对其不足创新地提出了改进型的边缘检测电路,通过对它们的仿真与性能进行分析对比,验证了本文提出的改进型边缘检测电路性能的优越性,并且在分析和设计该两种模型内部每一部分电路时都一直采用对比的方法。同时在FPGA的通用平台上,运用Verilog HDL编程语言实现了整个图像分割提取系统的关键模块的设计,并在开发环境Quartus II下,对模块进行波形仿真从而验证设计结果。这些关键模块包括Sobel检测算子、判断器、片上存储器等。硬件电路主要是采用Altera公司的Stratix II系列的FPGA芯片。图像分割提取技术作为数字图像处理中的关键技术之一,必将在未来数字图像处理领域得到更为广泛的关注。更多还原

【Abstract】 With the development of times,the structure of Digital Image Segmentation system becomes more and more complex and needs higher image processing speed.Traditional digital image segmentation systerm usually use Universal Microprocessor chip,but sometimes,the time requestment is very rigorous in image processing,if we use the Universal Microprocessor chip in the Digital Image Segmentation system,the systerm can not finish the necessary operation in the limited time.So,it’s necessary to design a special hardware logic circuit with high processing speed in the high speed FPGA chip for the operation.This paper introduces the deep research of the basic theory about image segmentation and their corresponding system cricuit, and puts forword the scheme of Digital Image Segmentation systerm with three steps:image edge detection,distance transform and template matching,as the limits of the experimental conditions and time,this paper has achieved the detialed designing process of the two front steps.And for the problem of pixel value data parallel importation in the image edge detection cricuit,this paper has added data“serial to parallel”cricuit to solve it, also has given the detailed design process and preformance analysis of the cricuit.So,the top-level system is composed of data“serial to parallel”cricuit,image edge detection cricuit and diatance transform cricuit.In the design process of image edge detection cricuit,I have fully analyse the merits and demerits of the circuit which is designed by predecessors,for its shortcomings,I have given an improved edge detection circuit.Through analysing and comparing their simulation and performance,I have presented the superiority of the improved edge detection circuit in this paper.And during the analysis and design of each part in the two module cricuits,this paper had used the compared method. The key modules of holistic image segmenttation were built based on the universal platform of FPGA using Verilog HDL,all the design of these modules can be simulated under the simulation environment of Quartus II . These modules include sobel detection operator,judge and on-chip memory and so on.The hardware electric circuits were mainly based on FPGA, the Series of Stratix II produced by Altera.As one of the key technologies in digital image procesing,the image segmentation will get more extensive attention.更多还原