基于Wilkinson合成器的LINC系统效率优化实现

【作者】 杨玲；

【导师】 何松柏；

【作者基本信息】 电子科技大学 ， 电路与系统， 2010， 硕士

【摘要】 第三代移动通信普遍采用数字多电平调制技术及多载波发射技术以提高频谱利用率,由此带来的信号峰均比增加对发射机各模块的线性度提出了很高的要求。LINC是一种发射机线性化结构,通过信号分离将变包络信号转变为两路恒包络异相信号规避了对功放的高线性要求。由于采用高效率功放对信号分别放大再合成,这种结构具有很高的理论效率。但实际应用中,合成器的工作特性却使系统效率远远低于预期值。本文从Wilkinson功率合成器的工作特性分析出发,通过对影响合成器瞬时效率因素的深入推导,将峰均比降低技术和非单一门限信号分离技术相结合形成LINC系统效率改善方案。通过对该方案具体模块的理论推导和仿真分析确定了各模块的具体实现方案及系统数据结构。在峰均比降低模块的设计中,本文选择极性削波方案作为实现结构,并采用内插级联滤波器取代一般的低通滤波器,降低了系统的硬件资源消耗。流水线技术和基于简化查找表技术的非单一门限信号分离方案,提高了信号处理速度并进一步节约了硬件资源。本论文采用Verilog HDL语言作为非单一门限信号分离模块及削波模块的设计语言,通过仿真与适配,详细论述了系统整体框架及模块设计,成功的实现了系统的效率改善,根据仿真和实验结果这种效率提高方案能将系统效率由原来的9.8%提高到33.05%。由于系统的硬件资源和个人时间因素的限制,该合成器效率优化方案还有待改进的地方,例如峰均比降低模块中滤波器对峰值信号的再生问题以及解决这种问题的方法等。本人下一步需要做的工作就是进一步优化峰均比降低模块的结构,并将其性能加以改善。更多还原

【Abstract】 Digital multi-level modulation techniques and multi-carrier technology are employed in all standards of the 3rd generation communication system to improve spectrum efficiency. These techniques cause a sharp increase in signal PAPR and have a high demand of power amplifier linearity. LINC (LInear amplification using Non-linear Components) is a linear transmitter architecture. By separated the phase- and magnitude-modulated signal into two constant envelopes, this architecture evade the high demand of amplifier linearity and can employ high efficiently PA. Therefore the theoretical efficiency of LINC amplifier can achieve 100%. However in practical application, the system efficiency is determined not only by amplifier but also by combiner, the working characteristics of combiner will led the system actual performance much lower than theoretical efficiency.This paper has analyzed the characteristics of Wilkinson power combiner and proposed a system efficiency improvement project based on PAPR (Peak to Average Power Ratio) reduction techniques and non-single threshold SCS architecture. After mathematical reasoning and simulation analysis, concrete implementation scheme and system data structure have been established.In the PAPR reduction module, polar clipping scheme and cascade interpolation filter has been employed to reduce system hardware resource consumption. Pipeline technology and simplified look-up-table improved the PAPR reduction module and non-single threshold SCS module’s signal processing speed and saved the system hardware resource consumption further. This paper adopted Verilog HDL as module design language. By simulation and adaptation, this architecture improved system efficiency successfully. According to the simulation and experimental results, this scheme could improve the system efficiency from 9.8% to33.05%.For the shortage of system hardware resource and the complexity of design, there were still something else have not been finished completely, for example the signal peak regeneration created by filter and how to reduce this effect etc. The next work of this paper is to further optimize the PAPR reduction module’s structure to improve its performance.更多还原