节点文献
LDPC码在COFDM通信系统下的研究与实现
【作者】 曹飞；
【导师】 张义德；
【作者基本信息】 电子科技大学 ， 信号与信息处理， 2010， 硕士
【摘要】 近年来,低密度奇偶校验(Low Density Parity Check LDPC)码作为一种可以接近香农极限性能的纠错码技术,逐渐成为信道编码理论研究的热点,在无线通信、深空通信、光和磁记录等领域得到广泛应用。随着下一代无线通信系统的研究,具有超强纠错性能的LDPC码技术和频谱利用率高、抗干扰能力强的OFDM技术,成为提高通信质量和数据传输速率的两大关键技术,受到人们的广泛关注。为此,本文研究与分析了LDPC码的编译码算法,并结合OFDM系统探讨和分析了改进型LDPC-OFDM方案,最后设计与实现了准循环LDPC码的译码器。基于以上思路,现将本文的主要工作归纳如下:(1) LDPC码编译码算法的研究分析。首先阐述了线性分组码的基本原理;其次,重点介绍了LDPC码的定义、几种重要的LDPC码构造和编码算法;最后,分析了LDPC码的基本译码原理和常用算法,同时重点研究和分析了概率域BP算法、对数域BP算法以及基于校验信息修正处理方式的BP-Based算法、Normalized BP-Based算法和Offset BP-Based算法,并对这五种译码算法的纠错性能和译码复杂度进行比较论证,选择适合硬件实现的译码方案。(2) LDPC码在OFDM通信系统中的应用与性能分析。首先,详细分析了OFDM系统特征;其次,从理论上对自适应调制技术、自适应比特分配、自适应功率分配技术以及信道估计技术进行深入研究;最后,结合LDPC码技术,针对通用LDPC-OFDM通信系统缺陷,提出改进型LDPC-OFDM方案,同时仿真并分析了LDPC码技术对该方案系统性能的影响。仿真结果表明,将LDPC码应用于该方案中可以获得很大的性能提升,为适用于未来宽带无线通信系统的LDPC-OFDM系统提供了一个很好的参考方案。(3)准循环LDPC码译码器的FPGA实现。针对传统译码器架构方案的缺陷,提出一种改进型部分并行译码器架构,系统采用自顶向下的设计方式,使用VHDL硬件描述语言进行RTL级描述,采用Altera公司的Quartus II软件进行综合、布局布线,最终在Cyclone II EP2C70F896C6 FPGA芯片平台上完成设计实现与功能和时序验证。同时,对于给定码长码型的QC-LDPC码,本文提出了提高译码器吞吐率的两种有效途径:流水线处理和折叠算法。实验结果表明,该译码器具有时序控制简单、译码时延小和资源利用率高的特点。当迭代次数为10次,系统时钟为190.99MHz时,基于折叠算法的改进型(1536,3,6)规则QC-LDPC码译码器的吞吐率可达104.18 M,基本可以满足未来宽带无线通信系统的吞吐率要求。
【Abstract】 Recently, as an error-correcting code technology with performance closed to Shannon limit, low density parity check code has gradually became a hot research in channel coding theory and widely applied in wireless communications, deep space communications, optical and magnetic recording fields. With the research of the next-generation wireless communication systems, low-density parity-check code technology with the superior performance of error correction and orthogonal frequency division multiplex technology that possesses high bandwidth efficiency and strong ability of anti-interference, have raised the communication quality and the data rate, which have received great attention. So, in this dissertation, encoding and decoding algorithms of LDPC code are studied, an improved LDPC-OFDM model is analyzed and then a quasi-cyclic LDPC codes decoder is also implemented.Based on these ideas, the main work is summarized as follow in this dissertation:(1) The research of encoding and decoding algorithms of LDPC code. First, the basic principle of linear block codes is introduced briefly. Second, the definition of LDPC code and several important structure and encoding algorithms are studied. Finally, the basic principle of decoding algorithms are analyzed, especially BP algorithm, log-BP algorithm and BP-Based algorithm, Normalized BP-Based algorithm and offset BP-Based algorithm that based on check information revised approach. And then the correcting performance and decoding complexity are balanced for picking out the most suitable algorithm for implementation.(2) The application and performance analysis of LDPC code in OFDM communication system. First of all, the characteristics of OFDM system are analyzed. Secondly, several improved technologies are studied in depth, such as adaptive modulation technology, adaptive bit allocation technology, adaptive power allocation technology and channel estimation technology. Finally, aiming to the defects of universal LDPC-OFDM model, an improved LDPC-OFDM model is proposed, and then its performance impaction is also analyzed by simulation. The simulation results show that LDPC-OFDM model has good performance, and apply a reference to the future broadband wireless communication systems using LDPC-OFDM model. (3) The FPGA implementation of quasi-cyclic LDPC decoder. Aiming to the shortcomings of the tradition decoder architecture, the improved partially-paralle decoder architecture is proposed, implemented and verified on the device Altera Cyclone II EP2C70F896C6. And for a given quasi-cyclic LDPC code, two effective ways (pipeline processing and scheduling algorithm) to improve the decoder throughput are proposed in this dissertation. The experimental results show that the decoder possesses simple logic control, low time delay and high resource using. By performing maximum 10 decoding iteration at 190.99MHz, the improved decoder that based on scheduling algorithm, could achieve a maximum bit throughout of 104.18Mbps to basically meet the requirement of the future broadband wireless communication systems.