【作者】 于斌；

【导师】 徐国栋；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 微小卫星是目前航天器发展的一个重要方向。作为现代微小卫星的关键部分,姿态控制系统显得更为重要。姿态控制系统从传统的以通用处理器为基础的软件执行方式,到专用集成电路ASIC为代表的硬件执行方式,在性能和设计周期方面难以平衡。以FPGA为代表的可重构计算技术填补了两者之间的空白。可重构计算将算法在FPGA上实现,可以获得非常高的性能。同时,系统可以根据目标算法的不同,动态的调整硬件,具有更好的灵活性和适应性,获得了越来越广泛的应用。哈工大卫星所的时变计算机项目依据可重构计算技术,需要对卫星的不同控制模式进行硬件设计。本文设计的对象是姿态控制系统的中一个控制模式——对地定向控制模式。设计的目标是完成对地定向控制算法的硬件设计,并在FPGA中实现。设计的内容主要包括基本运算单元和算法功能单元的设计。基本运算单元包括浮点加法器、乘法器,并主要对浮点三角函数的硬件计算进行了设计。算法功能单元用来完成软件部分的算法。由于算法中一些功能函数在不同的模式中是通用的,在设计过程中,注意保留了这些功能函数的独立性,以便在其它的控制算法中可以复用。设计最终通过功能和时序仿真,并在FPGA上正常工作。设计共占用ALU5432个,寄存器1888个,理论上可以工作的最高频率是22.51MHz,硬件部分完成一次运算需要866个时钟周期。更多还原

【Abstract】 The development of microsatellite is a significant trend in the aerospace area. As a key section of microsatellite, the attitude control system will be more and more important. However neither the software execution mode based on general purpose processor(GPP) or hardware execution mode based on ASIC gets a poise of the capability and design cycle. The reconfigurable computing mode based-on FPGA fills the gap between GPP and ASIC. The reconfigurable computing system often implements algorithms on hardware and performs well. Meanwhile, the system will adjust its hardware dynamically according to the algorithm’s difference. The reconfigurable computing could achieve good flexibility and adaptability, so it is spreading widely.The object designed in the paper is one of control models of an Attitude Control system that the orientation control model to ground. And the target is to complete the hardware design of an orientation control algorithm to ground and have the algorithm implanted in FPGA, and the content consists of the design of a basic arithmetic unit and an algorithm functional unit. The basic arithmetic unit comprises floating point adder and multiplier. Besides, the hardware calculation of floating point triangle function is particularly designed. The algorithm functional unit is used to realize the algorithm of software. Some of the performance functions in algorithms which are general in different models are capable of being reused in other algorithms, for the independence of which are retained attentively in design.The function simulation and the timing simulation of the design that works properly in FPGA are fulfilled at last. Totally, the design occupies 5432 ALUs and 1888 registers with a maximum operating frequency of 22.51MHz from theory, and the hardware processes one calculation in 866 clock cycles.更多还原