【作者】 姜申飞；

【导师】 戴庆元；

【作者基本信息】 上海交通大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 在混合信号集成电路系统中,模数转换器(ADC)是一个关键的模块。许多现代应用,如高分辨率图像、视频处理及无线通信等,都要求具有高采样率、高精度的模数转换器。流水线结构ADC具有能同时实现高采样速率和高分辨率的特点。对于10bit, 1MSample/s以上的ADC系统而言,流水线结构是一种合适的设计方案。本篇论文在分析了常见高速模数转换器结构的基础上,基于台积电(TSMC) 0.25um CMOS工艺,采用流水线结构设计完成了一个10位精度100MHz采样频率的模数转换器。该模数转换器采用采样保持电路、八级1.5位和最后一级2位子模数转换器的结构,电路使用全差分和开关电容电路技术。本文讨论了流水线模数转换器的误差以及精度提高技术如数字校正、模拟校正、电容平均技术。设计了基准电压源、高速比较器、运算放大器以及时钟产生电路等电路模块。为了有效的提高流水线模数转换器的转换速度,可以采用并行结构,本文对此进行了探索。并行结构的关键是怎么样提高通道间的匹配度,这直接影响到我们可以得到的最高分辨率。本文分析讨论了通道间失调、增益失配、时序失配,采用了双采样和运算放大器共用技术。此外,本文还对芯片的版图布局、匹配设计等进行了研究,亦对芯片的测试技术进行了有益的探索。芯片采用台积电(TSMC)0.25um,混合信号1P5M+/2P5M 2.5V/3.3V CMOS工艺,该工艺提供MIM结构电容。电路典型工作电压为2.5V,在室温下,输入信号为5MHz采样频率100MHz时信号噪声失真比为59.7dB,功耗为102.6mW。更多还原

【Abstract】 In mixed signal systems, Analog-to-Digital Converter (ADC) is a crucial portion. In many application areas such as high definition image, video signal processing and wireless communication, it keeps demanding high sample speed and high resolution of monolithic ADC. The pipelined ADC architecture has the characteristics of high sampling rate as well as high resolution. Generally, the pipelined architecture is most appropriate design plan for ADC systems beyond 10bit and 1 MSamples/s.Based on the analysis of some common high-speed ADC architectures, this thesis presents a 10-bit, 100 Msamples/s pipelined ADC using TSMC 0.25um CMOS process.It’s composed of a sample-and-hold circuit, eight stages with 1.5bit per stage, and a 2 bit flash ADC as last stage. This thesis talks about the error source of pipelined ADC and calibration techniques such as digital self-calibration, analog correction and background calibration. Designing a reference voltage and current based on bandgap, high-speed comparator, operational amplifier sample-hold circuit and clock generation circuit. For the purpose of raising the sample speed, we propose a parallel pipelined ADC. The key factor of parallel pipelined ADC is match between channels, which influences the effective resolution of ADC directly. We discuss the channel offset, channel gain mismatch and timing mismatch. And we propose the techniques of double sampling and OTA sharing.This thesis also discusses the place and match of the chip’s layout. And it talks about the test methods for ADC.The ADC’s design is based on the TSMC 0.25um, mixed signal 1P5M+/2P5M, 2.5V/3.3V CMOS process, which provide metal-insulator-metal capacitor. It works at 2.5V supply voltage, with room temperature, 100MHz sampling frequency, the input signal frequency 1MHZ, it achieves SNDR of 59.7dB, and power consumption is 102.6 mW.更多还原