【作者】 雷恺；

【导师】 冯军；

【作者基本信息】 东南大学 ， 电路与系统， 2005， 硕士

【摘要】 随着社会的发展,信息交换量与日俱增。近年来,以光波为载体、光纤为传输媒质的光纤通信异军突起,发展十分迅速,已成为信息高速公路的主体。光纤通信适用于多种综合数据业务,具有容量大、传输距离远、节省能源、抗干扰、抗辐射等诸多优点,发展势头迅猛,是未来宽带网络的发展方向。开发具有自主知识产权、用于光纤传输的高速集成电路对我国信息化建设具有重大意义。用于光纤传输系统的光发射芯片包括复接器和激光驱动器两块关键电路。作为光发射芯片的关键电路,激光驱动器电路的作用是提供一定的增益,放大复接器输出的高速信号,驱动后面的激光二极管。由于它是光纤传输系统中实现从数字信号向模拟信号转变、电压信号向电流信号转变、电信号向光信号转变的关键电路,因此在国内外都得到了广泛而深入的研究。本论文介绍的激光驱动器电路和单片集成的光发射芯片基于TSMC 0.18um CMOS工艺,适用于光纤通信系统STM-64速率级。激光驱动器电路设计的难点在于电路的大电流输出导致管子自身电容对电路工作速度的影响非常明显;另外本电路采用了TSMC 0.18μm CMOS标准工艺,故经典的差分放大器接源极跟随器的级联结构无法采用。文章按照电路设计、版图设计、工艺流片到芯片测试的顺序详细介绍了上述电路的设计过程及最终的测试结果。本次设计的激光驱动器电路采用直接耦合的两级差分放大器结构,电路中采用了并联峰化技术和放大级直接耦合技术以扩展带宽,降低功耗。在片测试显示该芯片在1.7V电源电压下,最高工作速率可达11 Gbit/s。输入速率为10Gb/s、单端峰峰值为0.3 V的信号时,50?负载上的输出电压单端峰峰值超过电源电压。激光驱动器电路功耗约为77.4 mW,芯片面积为0.94*1.25mm2。电路一次性流片成功,测试结果显示已达到世界同类集成电路中的先进水平。单片集成的光发射芯片后仿真结果表明:在1.8V电源电压作用下,该电路可工作在10.5Gb/s速率以上。输入四路单端峰峰值为0.2 V的10Gb/s信号时,单端50?负载上的复接输出电压单端峰峰值可达到1.6V以上。单片集成电路功耗约为230mW,芯片面积1.77*0.94 mm2。更多还原

【Abstract】 With the rapid development of telecommunication networks、computer networks and Internet, it is urgent to build information super-highway. Optic-fiber communication systems are the principal parts of information super-highway for its merits such as great capacity、long transmit distance、economizing energy source、anti interference and anti radiation etc. Thus, it is very important to design high speed integrated circuits for optical transmission systems with independent property.In the building blocks of an optical transmission system, the transceiver circuit is in the transmit direction. And it including two critical parts which are 4:1 multiplexer circuit(MUX) and the laser diode driver(LDD).The LDD is used to provide enough gain to magnify input signal. Because it is the critical part to change the digital signal to analog, voltage to current so it is one of the hot topics of researches.This paper introduces the design of a 10 Gbit/s laser diode driver circuit to be fabricated in 0.18 um CMOS technology for SDH STM-64. The difficulty of design focus on how to decrease the parasitical capacitance and which architecture can be adopted. In this paper, firstly the knowledge about SDH transmission system is introduced; subsequently the design procedure and test results are presented.Employing two stages of differential amplifiers directly, the circuit can amplify the input differential signal amplitude from 0.3V to 1.7V on a 50? output resistance at 10 Gb/s. the highest frequency the circuit can work is 11Gb/s, with the total power consumption is about 77.4mW,and the chip size is 0.94*1.25mm2。The test results prove that the LDD performance has reach advanced level.The design of a transceiver circuit at 10 Gb/s will be fabricated with 0.18 um CMOS technology. The post simulation show that the circuit can amplify the input signal amplitude from 0.2V to 1.4V on a 50? output resistance at 10.5Gb/s, with the total power consumption is about 230mW.The chip size is about 1.77*0.94 mm~2.更多还原