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降低接收机ADC精度的数字补偿方法的研究

Digital Compensation Method for Reducing the ADC Resolution in Wireless Communication Receiver

【作者】 冯晓东

【导师】 马骏; 贺光辉;

【作者基本信息】 上海交通大学 , 电路与系统, 2011, 硕士

【摘要】 近些年兴起的60GHz毫米波通信技术因为其数Gigabit的传输速率引起了无线通信领域的广泛关注,60Ghz毫米波通信技术使得Gigabit以太网和高清数字多媒体接口等应用的无线传输成为可能。不过60GHz毫米波通信技术也面临着一系列问题,其中一个比较关键的技术难点是设计高精度高采样率的ADC(Analog to Digital Converter,模拟到数字转换器),这样的ADC往往设计复杂度高、功耗大。同样的问题也存在于UWB(Ultra Wideband,超宽带)通信系统中。无线通信信号传输过程中所经历的信道干扰使得接收端信号的动态范围扩大,这是造成接收机ADC高精度的主要原因。在各种信道干扰中一个比较重要的干扰是多径干扰。本文对频率选择性衰落信道进行了深入分析,并对接收机结构进行研究,提出了一种用数模信号混合处理的均衡器来降低频率选择性衰落信道中接收机ADC的精度要求。该均衡器结构以引入一个高精度高采样率的DAC(Digital to Analog Converter,数字到模拟转换器)为代价,在不改变接收机性能的情况下将ADC的采样精度降低2个比特;在误码率、收敛速度等性能上均比同精度的全数字均衡器有了很大提高。进一步,文章对该结构进行了优化,仅把补偿信号的高比特位的值转换到模拟域,将引入的DAC的精度降低到2~3个比特,从而进一步降低了该结构的设计复杂度和功耗。

【Abstract】 The recent 60Ghz mm-wave technology opens a new era for multi-Gigabit wireless communication systems for its Giga bit per second transmission speed. This enables the transmission of Gigabit-per-second applications like the transmission of uncompressed high definition video and Giga-bit Ethernet. However, 60Ghz mm-wave technology faces a series of problems and one critical challenge is to design high-speed, high-precision Analog-to-Digital Converter (ADC) which is either hard to design or power hungry.The signal received by the ADC at the receiver side is always has a large dynamic range than the original because of the various interference of the wireless path and this is the main reason to make the resolution of the ADC be high. In all kinds of interference, multipath effect contributes much to the received signal. In this dissertation, we proposed a mixed-signal equalizer for high data rate wireless receivers to deal with the frequency selective fading effect based on the study of the frequency selective fading channel and the receiver structure. Though this structure, the resolution requirement of the ADC is reduce by nearly two-bits while maintain the same performance. The only expense is to introduce another high-speed, high-resolution DAC. Optimizations are conducted to the proposed structure to reduce the resolution of the DAC to further reduce the design complexity and power consumption.

【关键词】 数模转换器60Ghz均衡器
【Key words】 ADC60Ghzequalizer
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