【作者】 孙黎明；

【导师】 王伟；

【作者基本信息】 西安工业大学 ， 光学工程， 2011， 硕士

【摘要】 高帧频相机能够对高速运动物体进行捕获、记录,通过分析视频信息可以研究物体的运动规律和和细节信息,它被广泛应用于航空、航天及兵器等领域。本文以某型战机舱室仪表和舱外导弹发射状态监控为背景,针对拍摄过程存在帧频高、图像噪声大、数据量大等问题,设计了一种高帧频相机图像处理系统。本文重点研究内容包括三部分：高帧频图像采集单元、图像预处理单元和视频图像编码压缩单元。高帧频图像采集单元采用Cypress公司高速CMOS图像传感器LUPA-300,控制单元采用XILINX公司的FPGA,利用Verilog硬件描述语言编写程序,采用了自顶向下的设计方法,设计了三个模块,分别为CMOS图像传感器配置模块、图像缓存模块和Camera Link传输接口模块。每个功能模块独立设计,通过顶层模块连接,并在Modelsim软件中进行仿真。图像预处理单元主要分析CMOS图像传感器所成图像噪声特性,研究了消除CMOS图像传感器固定模式噪声的算法和分段两点非均匀校正算法,改进了传统的中值滤波算法,利用Verilog硬件描述语言编制了中值滤波程序,并在FPGA中实现中值滤波算法的硬件执行。图像编码压缩单元主要研究了基于MPEG-4标准的视频编码压缩算法。运用视频管理器VCM控制编码器,消除图像的空间冗余和时间冗余信息,利用VC++语言编写了视频编码压缩程序。最终建立了图像处理系统,实验表明该系统在时钟50MHz,最大分辨率640x480情况下,拍摄速度可以达到每秒155帧,通过预处理能够有效消除图像噪声,通过视频压缩管理器VCM实现了基于MPEG-4的视频编码压缩。更多还原

【Abstract】 High frame frequency camera can capture and record high-speed target. It can be used to analyze moving mechanism and details of the target by the recorded video, so it is applied widely in high-speed measurement field, such as aviation, aerospace and weapons. For supervising the instrument panel in the cabin and recording of missile lunching state outside the cabin of fighter, a high frame frequency CMOS camera image processing system was designed. This system was designed mainly to accomplish the problem of high frame rate, huge image noise, mass data.Main research contents of this dissertation included three parts as follows:high frame frequency image acquisition unit, image pre-processing unit and video coding unit.High speed CMOS image sensor LUPA-300 of Cypress Corporation was used in image unit and the FPGA of Xilinx Corporation was applied in controlling unit. CMOS image sensor configuration module, image buffer module and Camera Link high-speed data interface module were designed through Verilog HDL and top-down design methodology. Each module was designed respectively and connected through the top-level module, and it was simulated in Modelsim software.In image pre-processing unit, the image noise characteristics of the CMOS sensor was analyzed. The fixed pattern noise eliminating algorithm and two point multi-stage non-uniformity correction algorithm were researched. Improved median filtering algorithm program used Verilog HDL was implemented in FPGA.In video coding unit, the video coding compression algorithm based on MPEG-4 was analyzed. The coder controlled by VCM (video compression manager) was used to eliminate time and spatial redundancy. The program was implemented by VC++.At last, high frame frequency CMOS camera image processing system is established. Experiment results show the frame can reach 155 fps in a format of 640* 480 with the clock of 50 MHz. The image noise is eliminated effectively by the pre-processing unit. Then the video compression based on MPEG-4 is implemented by VCM.更多还原