节点文献
片上网络中的同步与仲裁技术研究
The Research of Synchronization and Arbitration in Network on Chip
【作者】 刘宇;
【导师】 杨银堂;
【作者基本信息】 西安电子科技大学 , 微电子与固体电子学, 2011, 硕士
【摘要】 随着半导体技术和SoC技术的不断发展,片上系统已经开始朝多核化和异构化的方向发展,而当前片上系统设计所广泛采用的共享总线结构由于时钟问题而逐渐成为制约SoC系统性能的主要瓶颈,已经无法满足大规模片上通信的需要。因此可以借鉴计算机网络的互连概念,把互连网络应用于片上系统,以解决片上组件之间的各种通信问题。片上网络(NOC-Network On Chip)技术因其所具有的高并发性、高可靠性、高重用性等特点被认为是下一代大规模片上多核互连技术。片上网络克服了总线结构可扩展性不足的缺点,为10亿晶体管时代提供了一种可行的片上系统通信机制。本论文主要对片上网络中的同步和仲裁技术进行了系统研究。本文对片上网络中的同步技术进行了讨论与研究。首先讨论了同步技术中最主要的问题—亚稳态的产生原理;然后研究了双触发器法和异步FIFO等同步技术,并采用开发工具ModelSim 6.2和Quartus II,结合硬件描述语言Verilog对基于格雷码的异步FIFO进行了仿真和综合;最后研究了两种全局异步局部同步系统中常见的同步技术—可停时钟技术和本地延迟锁存技术,并对其工作原理和时序进行了分析,同时也给出了具体的电路结构,并对电路进行了仿真验证。本文的另一个研究重点是片上网络中的仲裁技术。首先介绍了一些传统的仲裁器,如网格、树型、令牌环等;然后针对这些传统仲裁器无法保证顺序仲裁的问题,本文提出了一种新型的顺序仲裁器,并利用Cadence对其进行了仿真验证;最后对静态优先级仲裁器和动态优先级仲裁器进行了研究,分别给出了这两种仲裁器的电路结构,对其中起到识别优先级的优先级模块进行了设计,提出了一种树型的仲裁结构,并使用Cadence软件对动态仲裁器进行了仿真验证。
【Abstract】 With the development of semiconductor technology, System on Chip has developed towards more processors and heterogeneity. While the shared bus architecture applied widely in the SoC presently gradually becomes the main bottleneck which restricts the system performance of CMP and can not meet the requirement of SoC. Therefore, the interconnection network is used for the SoC designs in order to resolve the communication between the on chip components, namely Network on Chip (NoC). Due to the characteristics of supporting many users to visit at the same time, high reliability and reusability, NoC is thought to be desired technology of multiprocessors.This thesis researches the technology of synchronization and arbitration.First, the reason of metastable state is introduced. To overcome the metastable state, the basic methods, two flip-flop synchronizer and asynchronous FIFO, are presented. And a asynchronous FIFO based on Grey code is developed and simulated with Modelsim 6.2. At last, two common synchronizer in GALS system are introduced—stoppable clck and locally delayed latching. Their operation modes and time sequences are also analysed.Another research focus of this thesis is arbitration in NoC. I first introduce some basic arbiters, such as mesh, tree and token ring arbiter. According to the problem of not guaranteeing the correct arbitrationorder in these arbiters, a new asynchronous ordered arbiter is proposed. In addition, it is simulated and tested with Cadence tools. Then the priority arbiter is introduced, including static priority arbiter and dynamic priority arbiter. Their principles and schematics are also presented.
【Key words】 Network on Chip; Synchronizer; Stoppable clock; Ordered arbiter; Priority arbiter;