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CORDIC的IP核生成平台的设计与实现

Design and Implementation of IP Core Generator of CORDIC

【作者】 刘波

【导师】 黄秋元;

【作者基本信息】 武汉理工大学 , 通信与信息系统, 2010, 硕士

【摘要】 坐标旋转算法(Coordinate Rotational Digital Computer, CORDIC)是一种用迭代方式完成矢量旋转的方法,可用于三角函数、双曲线函数、平方根、对数、指数等一系列函数的运算。由于CORDIC算法中对数据的操作只有移位和加减,易于硬件实现,能够极大地降低设计的复杂度,因而被广泛应用于各种系统级芯片(System On Chip, SOC)中。而随着电路规模和复杂度的不断增加,以及越来越紧迫的项目开发时间,基于IP核重用的系统设计方法逐渐成为了SOC设计的主流。本课题以三网合一项目HiNOC(High Performance Network Over Coax)为依托,首先完成了系统中数字下变频、频率偏移校正等应用场合下的CORDIC电路的设计,使用仿真工具LDV(Logic Design and Verification)对所设计的CORDIC电路进行了功能验证,并采用FPGA芯片进行了实现和测试。然后通过比较不同应用场合中的CORDIC电路的结构,针对不同迭代次数、不同运算精度和不同实现架构等构造出了CORDIC的IP核生成平台。为了验证生成的CORDIC软核的功能,设计出了一个可配置的一致性验证平台。使用本文中设计的IP核生成平台,用户只需设置相关的参数然后运行该平台,就能得到经过验证功能正确的CORDIC软核,既可以集成到SOC中,也可以用于FPGA设计中。可配置的一致性验证平台可以根据用户设置完成对不同CORDIC电路的功能验证,从而大大缩短电路的设计和验证时间,使设计人员可以更多地关注于系统的整体设计。本文所设计的CORDIC电路具有以下优点:(1)通过对输入的角度进行预处理,将CORDIC的运算范围扩大到了整个坐标系;(2)简化了校正因子的运算,进一步节省了资源。本文中所采用的思想对于类似的常用电路的设计具有可借鉴性,可以根据实际的应用场合设计出相似的IP核生成平台,从而能够在较短的时间内得到功能正确的IP核用于系统集成,加快项目的开发进度。

【Abstract】 CORDIC is an algorithm employs multiple iterations to complete vector rotation which can be used to calculate many functions such as trigonometric functions, hyperbolic functions, the square root, logarithmic, exponential and so on. Because the data operations in CORDIC algorithm just contain addition, subtraction and shift which are easy to be implemented by hardware, and greatly reduces the complexity of design, so it is widely used in a variety of SoC (System On Chip). And with the scale and complexity of the circuits increasing, system designed based on reusable IP is becoming more and more popular.This paper is based on the project HiNOC, the design of the CORDIC circuits used in digital down conversion and frequency offset correction are completed first, then use the simulation tool LDV verify the functionality and implemented with FPGA. And then, after deeply study the structure and technical details of CORDIC circuit design, construct an IP core generator of CORDIC for different iteration times, different computing precision, as well as the realization structure of different applications. A flexible user-configurable consistency verification platform is also designed to verify the CORDIC soft IP.Use the platform designed in this paper, after simply set some parameters such as work modes, iteration times, pipeline stages, and so on and run the platform, uers can get a verified CORDIC module which can be used both in SOC and FPGA design. The user-configurable consistency verification platform makes CORDIC circuit design and verification can be completed at the same time, significantly reduces the design time, so the engineers can focus more on the top design level.The CORDIC circuit designed in this paper has the following advantages:(1) extends the input angle to a complete cycle via coarse rotation; (2) simplifies the computing of the correction factor of overall iterations and greatly save the resources. The platform designed in this paper has a certain nature which can used by others, for a functional circuit block which complete certain function especially the ones which are used very often, engineers can design a similar common platform based on the actual applications. Then a verified and function correct IP core can be generated in a very short period of time and used for system integration, greatly speed up the schedule of the projects.

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