【作者】 杜路泉；

【导师】 王泽勇；

【作者基本信息】 西南交通大学 ， 物理电子学， 2008， 硕士

【摘要】 对弓网故障的检测是当今列车检测的一项重要任务。原始故障视频图像具有极大的数据量,使实时存储和传输故障视频图像极其困难。由于视频的数据量相当大,需要采用先进的视频编解码协议进行处理,进而实现检测现场的实时监控。H.264/AVC(Advanced Video Coding)作为MPEG-4的第10部分,因其具有超高的压缩效率、极好的网络亲和性,而被广泛研究与应用。H.264/AVC采用了先进的算法,主要有整数变换、1/4像素精度插值、多模式帧间预测、抗块效应滤波器和熵编码等。本文使用硬件描述语言Verilog,以红色飓风Ⅱ开发板作为硬件平台,在开发工具QUARTUSⅡ6.0和MODELSIM_SE 6.1B环境中完成软核的设计与仿真验证。以Altera公司的CycloneⅡFPGA(Field Programmable Gate Array)EP2C35F484C8作为核心芯片,实现视频图像采集、存储、显示以及实现H.264/AVC部分算法的基本系统。FPGA以其设计灵活、高速、具有丰富的布线资源等特性,逐渐成为许多系统设计的首选,尤其是与Verilog和VHDL等语言的结合,大大变革了电子系统的设计方法,加速了系统的设计进程。本文首先分析了FPGA的特点、设计流程、verilog语言等,然后对静态图像及视频图像的编解码进行详细的分析,比如H.264/AVC中的变换、量化、熵编码等;并以JM10.2为平台,运用H.264/AVC算法对视频序列进行大量的实验,对不同分辨率、量化步长、视频序列进行编解码以及对结果进行分析。接着以红色飓风Ⅱ开发板为平台,进行视频图像的采集存储、显示分析,其中详细分析了SAA7113的配置、CCD信号的A/D转换、I~2C总线、视频的数字化ITU-R BT.601标准介绍及视频同步信号的获取、基于SDRAM的视频帧存储、VGA显示控制设计;最后运用verilog语言实现H.264/AVC部分算法,并进行功能仿真,得到预计的效果。本文实现了整个视频信号的采集存储、显示流程,详细研究了H.264/AVC算法,并运用硬件语言实现了部分算法,对视频编解码芯片的设计具有一定的参考价值。更多还原

【Abstract】 The detection of catenary-pantograph malfunction is extremely significant in current train inspecting. The immense data of the original malfunctioned video image makes simultaneous storaging and transmissioning quite difficult. Because of immensity video images data, it needs advanced video coding and decoding protocol to process. So it can inspect malfunction place simultaneously.As the tenth part of MPEG-4, H.264/AVC has superhigh compress efficiency and excellent internet affinity, it is researched and applied widely. H.264/AVC has advanced algorithm. It has integer transform, quarter-pixel interpolation, multi-mode inter prediction, deblocking filter, entropy coding and so on.This paper uses Verilog HDL to design. With the hardware platform of the Red Cyclone II, it completed the design and the simulative confirmation of the soft core with the hardware descriptive language Verilog in the environment of the exploited tool QUARTUS2 6.0 and MODELSIM_SE6.1B. Based on EP2C35F484FC8 of Altera company’s Cyclone II chip FPGA, video capturing, display, some algorithm of H.264/AVC and transmission can be realized.With the outstanding characteristic of flexibility, high speed in design and a large quantity of line resource, FPGA becomes the top choice in various actual applications gradually, combining verilog and VHDL language, it makes great innovation to the design of electric system and make the process faster.In this paper, characteristic of FPGA, flow of design, verilog language were analysed firstly, then static images and video’s coding and decoding was analysed in detail, such as transform, quantization, entropy coding and so on; lots of experiments have been done by using H.264/AVC’s algorithm based on JM10.2 for different resolution, quantiser parameter, video, and the results of experiment were analysed in detail. Then video images were captured, storaged and displaied based on Red Cyclone II, however, the SAA7113 chip’s initializes , the analog to digitial transform of CCD’S signal, inter IC line were analysed. After that, ITU-R BT.601, video synchronization signal’s capture were finished. Then video images storage and the control design of VGA display have been done. Finally, some of H.264/AVC’s algorithm were achieved using VerilogHDL, after that function imitate has been done and got the result which were predicted before.In this paper, the whole flow of video signal’s capture, storage and display have been finished. Parts of H.264/AVC’s algorithm has been finished by using VerilogHDL. To some extent, this paper will be beneficial for the video coding and decoding of chip design.更多还原