【作者】 杨敏；

【导师】 陆锦辉； 顾斌；

【作者基本信息】 南京理工大学 ， 电子与通信工程， 2008， 硕士

【摘要】 数字滤波器是常用的数字信号处理系统。在软件无线电系统中,数字滤波器发挥非常关键的作用。现代通信设备要求大吞吐量信息的实时处理、便携式和低功耗的特点,对数字滤波器的效率提出了苛刻的要求,即要求处理速度尽可能高,电路面积尽可能小,消耗功率尽可能低。此三个要求必然相互对立,因此设计者往往使其相互妥协以满足用户要求。提高数字滤波器的效率,应该从两个方面入手。第一,研究数字滤波器的传递函数,以寻求最简捷的数学表达形式。级联积分一梳状滤波器是一种传递函数形式简捷,适用于软件无线电通信系统中处于高采样率的数字前端使用的高效抽取或内插滤波器。此外,半带滤波器是FIR滤波器中的一种抽头系数被简化的特殊的线性相位滤波器。第二,研究其实现结构,即实现传递函数的算法。分布式算法将乘累加运算中采样信号序列的对应二进制数据位形成地址,映射到数据表,其内容为各抽头系数的不同组合后的累加。这样免去了乘法运算,大大提高了运算的速度。多相结构将高速滤波器分解成多路低速子滤波器,从而降低了系统功耗。首先研究了软件无线电中广泛使用的级联积分梳状滤波器。其次研究了软件无线电中广泛使用的基于分布式算法的半带滤波器,研究了其传递函数及频率特性。最后研究了数字滤波器的多相结构。对其中涉及的各种类型滤波器,通过实例进行了基于Matlab的理论仿真、基于Modelsim的逻辑仿真和基于Quartus的FPGA实现的EDA仿真,得到了与理论吻合的波形和频谱,以及资源开销和功耗的仿真结果。更多还原

【Abstract】 Digital filters are commonly used DSP system. They play a key role in the processing of ommunication signal in SDR system. However, the modern communication system’s requirements of real time processing of large throughput of information, being handy and low power consumption, put forwards very stringent requirements on the efficiency of digital filters, which can be concluded as the highest operation speed, the smallest circuit area and the lowest power consumption. The three requirements mentioned above are, however, mutually contradictory, hence the designers usually make a tradeoff in order to satisfy the application requirement.There should be two ways as following aimed at raising the efficiency of digital filters.Firstly, study transfer function of digital filter to seek a simplest mathematical expression form. The cascaded integrator comb filter (CIC) is a sort of interpolation or decimation filter with an extremely reduced transfer function and very high operation efficiency. The another sort of filter is halfband (HB) filter which is a special linearly-phased filter, the tap coefficients of which are greatly reduced.Secondly, study the realization structure, i.e. the algorithm to realize the transfer function. Distribution Algorithm forms the corresponding binary bits of the sampled signal sequence in MAC operation into address, which maps into a table, the content of which are the accumulation of coefficients of various taps, thus avoiding the multiplication and raising the operation speed sharply. The polyphase structure decomposes the high-speeded filter into several parallel low-speeded subfilters, thus decreasing the system’s power consumption.Firstly the cascaded integrator comb filter are studied. Secondly the DA-based HB-filter, which is widely used in the SDR system, are studied, including transfer function and frequency characteristics. Finally the polyphase structure of digital filter are researched. Several instances of the filters and algorithms mentioned above are verified via Matlab-based theoretical simulation, Modelsim-based Logic simulation and Quartus-based EDA simulation of FPGA implementation, obtaining the simulation results of waveform ,spectrum, circuit consumption and power consumption, all of which fit the corresponding theory well.更多还原