【作者】 刘滔；

【导师】 李仁发； 付彬；

【作者基本信息】 湖南大学 ， 计算机科学与技术， 2009， 硕士

【摘要】 可重构片上系统将可编程逻辑器件、微处理器核及其他电路模块共同集成到单个芯片中,是一种兼具定制硬件的高性能和软件编程的灵活性的新型计算平台。在高运算需求的应用中,这一特性可较大幅度提升系统效能。但目前仍有两方面困难阻碍这类系统的广泛应用,它们是:1.编程困难传统的软件编程语言只能利用设计空间的时间维度,传统的硬件语言只能利用设计空间的空间维度。由于可重构片上系统能够同时在时间和空间维度编程,要实现对可重构计算系统资源的有效利用,需要应用程序员能够同时使用软硬件编程语言进行设计,并考虑动态重构以及软硬件通信的细节。2.设计困难按照传统协同设计方法学“先划分再实现”的步骤进行可重构片上系统的设计,必须考虑对硬件任务进行调度,才可能高效利用系统上的动态可重构资源;由于软硬件划分非常复杂,本身已是NP难问题,进行可重构片上系统设计要求设计人员具备丰富的经验和很高的专业素质。本文针对当前可重构片上系统对程序员编程不透明,且动态可重构资源难以有效利用这两个问题,提出并实现了一种支持软硬件协同设计的过程级统一编程模型。主要工作如下:1.完成了过程级统一编程模型的总体设计。确立了一个以软硬件协同函数库为基础的从系统功能描述到实现的动态软硬件划分流程,构建了支持应用程序开发和划分算法设计的软硬件协同设计集成开发环境。2.完成了软硬件协同函数库的设计和实例开发。该库被设计成“一个C语言接口对应软硬件两种实现”的方式,在为程序员系统描述提供统一易用的函数调用接口的同时为软硬件划分算法提供划分的对象。3.完成了动态链接控制的设计与实现。通过修改动态链接器,使其在程序运行时实时记录协同函数的调用、执行情况,并调用软硬件划分算法,根据划分的结果切换函数的软硬件执行方式。实例设计和实验结果表明,本模型能够方便程序员编写程序,程序在划分算法合理划分的支持下能够有效利用动态可重构资源并得到加速。更多还原

【Abstract】 Reconfigurable System-on-Chip (RSoC) integrates microprocessor, reconfigurable logic unit and other electronic modules into one chip. This kind of platform could provide high performance of costumed hardware and flexibility of software programming. In high-demanding computing applications, this feature can considerably improve system performance. But at present, there are still two difficulties in applying the new computing platform as follows:1. Programming is difficult. Traditional software programming language can only make use of time dimension of design space. And traditional hardware description language can only make use of spatial dimension of design space. But reconfigurable hardware can be programmed in both time and spatial dimensions. In order to achieve good utilization of reconfigurable resources, it requires programmer to be accomplished in hardware and software programming at the same time and to know the details of dynamic reconfiguration and communication between software and hardware.2. Co-design is difficult. Designing an RSoC according to the traditional co-design methodology of“partitioning before implementation”, the designer must consider the hardware tasks scheduling for making efficient use of dynamically reconfigurable resources. Since the problem of hardware/software partitioning is very complicated, this is an NP hard problem. Hence to fulfill this whole work should rely on rich experiences and professional skills of the designer.According to the difficulties above, Reconfigurable System-on-Chip is opaque to program, and the utilization of dynamically reconfigurable resources is in low efficiency. To address this issue, this paper proposes and implements a uniform function-level programming model which supports hardware/software co-design. The research work includes:1. Designed a function-level programming model. Established a dynamic hardware-software partitioning flow from system specification to system implementation, which is based on hardware/software co-function-library; Designed a hardware/software co-design integrated development environment for application development and hardware-software partitioning algorithm design.2. Designed hardware/software co-function-library and implemented some examples. The library has been designed as "a C language interface corresponding to software and hardware two implementations". It provides programmer with a unified easy-to-use function call interface, and also provides partitioning objects for partitioning algorithm.3. Designed and implemented dynamic link control scheme. Modified the dynamic linker, so that it will record the state of calling and execution of the co-functions when program is running, and switch the execution mode of the functions in real-time through calling hardware/software partitioning algorithm.Examples of the design and experimental results indicate that this model can facilitate the programming procedure. And under a reasonable partitioning algorithm, programs can effectively use the dynamically reconfigurable resources and its execution is accelerated.更多还原