面向卫星导航接收机应用的时钟源与模数转换器芯片设计

【作者】 叶鹏；

【导师】 文光俊；

【作者基本信息】 电子科技大学 ， 通信与信息系统， 2009， 硕士

【摘要】 锁相环是一种输出信号在频率和相位上能够与输入参考信号同步的电路,它是模拟及数模混合电路中一个基本的并且非常重要的电路模块。由于锁相环具有捕获、跟踪以及窄带滤波的能力,因此它被广泛地应用于航天、通信以及微处理器等许多领域。锁相环在微处理器领域中的一个重要应用就是为系统提供片内时钟,它是微处理器时钟电路中的核心模块。随着集成电路的发展以及SOC技术的出现,锁相环己经成为超大规模集成电路和模拟集成电路中一个必不可少的模块,因此对锁相环电路的研究和设计具有相当重要的意义。模数转换器是现代通信、雷达、声纳以及众多消费电子产品中的关键器件。作为模拟与数字电路的接口电路,高性能的模数转换器对设计系统的实现尤其重要,而当今科学技术的发展对模数转换器性能,特别是速度上的要求越来越高,甚至成为决定设备性能的关键因素。本文在分析了锁相环时钟源和模数转换器的基本原理和典型电路结构的基础上,设计了一个50MHz的时钟源电路和一个2Bits的模数转换器。将时钟源的时钟输出做为模数转换器的采样时钟。首先详细分析了锁相环和模数转换器的基本理论,并且使用Simulink对锁相环时钟源建立了时域模型来验证环路参数的正确性,然后在Cadence环境下,使用JAZZ 0.35um BiCMOS工艺对时钟源电路和模数转换器进行原理图设计,使用Virtuoso Layout XL进行版图设计,使用Spectre仿真软件进行仿真,性能达到预期目标,最终完成了整个设计工作。更多还原

【Abstract】 Phase-locked loop (PLL) is a circuit which can synchronize its output signal with an input reference signal in frequency and phase. It’s a fundamental and very important module in analog and mixed-signal integrated circuits. Because of its ability of tracking,acquisition and operating as a narrow-band filter, PLL is widely used in many fields such as astronautics, communication, microprocessor, and so on. One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a core module of microprocessor. With the development of integrated circuits and the emergence of SOC (System on a Chip) technology, PLL has played so important a role in VLSI circuits and analog integrated circuits that it is worth researching and esigning.Analog-to-digital (ADC) converter is the key device of advanced communication rada acoustic susceptance and many consume eletronics .As a special interface connects with analog and digital circuits, high performance analog-to-digital converter is more and more important in whole system design. Now the development of the technology has more need of the performance of the ADC,especially the speed. It even has become the key factor of the device performance.In the basic of the analyzing of PLL and ADC’s basic principle and typical schematics,this paper designs a 50MHz clock generator and a 2bits ADC.the sampling clock of ADC is the output clock of PLL.we analysis the principle of PLL and ADC detailly,and we construct a timimg model of PLL clock generator in SIMULINK to check whether the parameter of PLL is right.then the schematics of PLL and ADC are designed in cadence environment with JAZZ 0.35um BiCMOS process;the layouts of PLL and ADC are designed with Virtuoso Layout XL.we use the spectre tool to simulate the design.the results show that the performance of design is well.Finally,all works are completed.更多还原