NoC体系结构性能评估及通讯元件设计

【作者】 杨智峰；

【导师】 田泽；

【作者基本信息】 西北大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 目前,半导体的工艺节点已经减小到了50nm,单个芯片上可以集成的晶体管数目已经突破了10亿只。工艺的进步使得在单一芯片上实现具有复杂功能的系统有了可能。另一方面,消费者对于功能更加强大、规模更大的集成电路的需求不断增长,加之传统总线结构的SoC(片上系统)的弊端日益显露。在这样的背景下,人们借鉴计算机系统从单机到网络发展的历史经验,试图用基于通信的NoC(网络化芯片)来解决目前集成电路设计中遇到的问题。NoC的研究和应用目前尚处于起步阶段。其研究范围比较广泛,目前研究的主要内容有:拓扑结构、通讯协议、基础元件库和EDA实现理论与工具。本文在总结NoC理论体系的基础上,重点介绍NoC体系结构性能的评估和NoC通讯元件的设计。本文在分析了影响NoC体系结构性能的各种参数之后,介绍了用网络仿真软件NS2对几种常见拓扑结构的通信进行仿真的过程。作者用awk对仿真得出的trace文件进行了处理,得到了网络延迟、吞吐量和丢包率的定量值,并用绘图工具xgraph和gnuplot将其绘制出来进行了比较。另外,本文详细介绍了基于二维Mesh结构的NoC通讯元件——资源网络接口(RNI)和交换机(switch)的设计与仿真过程。作者用硬件描述语言(HDL)Verilog对其进行了寄存器传输级(RTL)代码的编写,并编写测试平台,用仿真软件Modelsim对其功能进行了仿真。仿真结果显示:此次设计的RNI和switch逻辑功能正确。更多还原

【Abstract】 At present, the technology node of semiconductor has reduced to 50nm and the number of transistors per chip has broken through 1 billion. The advancement of technology makes the accomplishment of complex system on single chip possible. On the other hand, the consumers’ demands for powerful and large integrated circuits(IC) are growing and the disadvantage of traditional bus based SoC(System on Chip) appears increasingly. In such background, people used the historical experience of the development of computer systems from stand-alone to networks for reference and try to resolve the problems in present IC design field by the NoC(Networks on Chip) which is based on communication.The researches and applications of NoC are just in the start-up phase now. The scope of the study is abroad. The main contents of NoC study include topology structures, communication protocols, basic component libraries and the implemental theory and tools by EDA. Based on the conclusion of the theoretical system, this paper focuses on the performance evaluation of NoC architecture and the design of communication components of NoC.After analyzing the performance metrics of NoC architecture, the paper introduces the simulation process of the communication in several ordinary topology structures using the network simulation software NS2. The author obtained the delay, throughput and packets loss rate after dealing with the trace file using awk and compared them by the drawing tools xgraph and gnuplot.In addition, the paper presents the design and simulation process of the NoC communication components - resource network interface (RNI) and switch based on the architecture of 2D Mesh topology. The author wrote the register transfer level(RTL) codes in hardware description language(HDL) Verilog for them, designed the test bench and simulated their functions using simulation software Modelsim. The results show that the logical functions of the RNI and switch are right.更多还原