深亚微米集成电路的低功耗设计

【作者】 陈志强；

【导师】 叶凡；

【作者基本信息】 复旦大学 ， 电子和通信工程， 2008， 硕士

【摘要】 工艺特征尺寸的日益减小使得集成电路在集成度和性能方面不断获得提高,但与此同时,系统复杂程度的提高以及各种移动设备的广泛使用,也使得电路功耗开始成为芯片设计发展的重要瓶颈之一。功耗不但直接影响芯片的封装形式与成本,而且过高的功耗将导致芯片温度的增加,直接决定着芯片的可靠性。此外,系统功耗的增加还将带来电迁移效应,电流密度增大等问题,使得芯片的稳定性进一步恶化,而这些影响反过来又会给电源供给的设计以及电路可靠性分析等诸多方面带来挑战。低功耗技术研究已显得越来越迫切,这些因素都迫使设计者越来越多地关注集成电路功耗的评估及优化方法的研究。文章首先阐述了本课题的研究背景,并对当前系统级芯片(SOC)低功耗技术的基础研究内容、主流的低功耗设计技术进行了总结。其后重点介绍了几种在标准单元中实现的低功耗方法,如用于多电源供给的电平转换器,带数据恢复的触发器以及体电压反偏置技术。更多还原

【Abstract】 With the descending of the process characteristic size, IC had improved greatly on the aspects of integration and performance. However with the improvement of the system complexity and the wide application of various mobile equipments, power consumption become an important bottleneck of chip design development. Power consumption not only affects chip package type and cost, also causes the increase of chip temperature, which will decide the reliability of chip directly. The increase of system power will bring about the issues on electron-mobility effect and increase in current density, resulting in the deterioration of chip stability. Furthermore, these phenomena will bring multitude of challenges into the design of power supply and analysis of circuit reliability. The research of low power technology is becoming more and more imminent. All these factors will force the designers to focus more and more research of evaluation and optimization on IC power consumption.This paper initially discusses the research background on the deep sub-micro low power chip design . Then the paper summarizes the fundamental research content of the most current SoC low power technology and mainstream low power design technology. This paper places latter emphasis on several low power techniques on standard cells, such as level shifter for multiple power supply, flip-flop with data retention capability, and back-bias technology.更多还原