【作者】 齐志强；

【导师】 葛建华；

【作者基本信息】 西安电子科技大学 ， 通信与信息系统， 2008， 硕士

【摘要】 本文针对中国数字电视地面传输标准(下文简称国标),研究支持全模式的低复杂度的调制器硬件实现方案。首先研究了适合国标的低密度校验(LDPC)码的编码方法,设计了一种可有效融合国标所支持的三种LDPC码率编码的实现方案,采用移位寄存器组进行编码,通过设计资源复用,使硬件资源消耗降低了约40%,并在FPGA(现场可编程门阵列)上实现。论文深入研究了3780点快速傅立叶变换(FFT)实现算法,在此基础上提出了一种精度高、占用资源较少的FPGA实现方案。通过对误差的分析和定点仿真,优化了算法、确定了比较合适的字长和巧妙利用国标中数据的信号结构使RAM的使用量降低了44%,成功地用FPGA实现了输出信噪比达61dB的3780点IFFT处理器。最后,在整体考虑了系统实现目标及功能等问题后,设计并实现了调制器的硬件平台。对硬件平台及调制器硬件程序的调试进行了说明,并对电路实现过程中遇到的问题及解决方法进行了总结。更多还原

【Abstract】 This dissertation focuses on the hardware implementation of the modulator in national DTTB(Digital Television Terrestrial Broadcasting) standard, and it presents a hardware implementation scheme which supports all the modes in DTTB standard with low complexity. We introduce an efficient encoding algorithm with shift register adder accumulator circuit based on the research of LDPC(Low-density Parity-check) coding. The scheme we present and implement can reduce about 40% of the logic cells in FPGA(Field Programmable Gate Array) due to the new method which can share the hardware resource in different LDPC encoding rates.We propose a hardware implementation structure for 3780-point FFT which has high precision and low complexity after traversing the FFT algorithms. By analysis of error and fix-point simulation, the algorithm is optimized and the length of byte is ascertained. By making use of the signal structure in DTTB standard skillfully, we reduce the use of RAM by 44% and implement the 3780-point IFFT in FPGA with the output SNR up to 61dB.Finally, we design and implement the hardware platform, considering the purpose and function of the modulator. The methods of debugging the programme and hardware platform are presented and the problems encountered and their solving methods are also included.更多还原