【作者】 何庆涛；

【导师】 葛建华；

【作者基本信息】 西安电子科技大学 ， 通信与信息系统， 2008， 硕士

【摘要】 本文采用理论分析和计算机仿真相结合的方法,在已有的理论基础上研究了低密度校验码编译码器的设计与实现问题,着重研究了准循环低密度校验码译码器的FPGA实现,完成了以下几个方面的工作:1.介绍了低密度校验码特别是准循环低密度校验码的相关概念,并归纳出了数字电视地面广播传输系统中用到的准循环低密度校验码的特点。2.介绍了用校验矩阵来实现低密度校验码快速编码的方法,分析了如何用移位寄存器在线性时间内完成准循环低密度校验码编码的问题,在此基础上给出了数字电视广播传输标准中准循环低密度校验码的编码实现方案。3.介绍了低密度校验码译码的置信传播算法,系统地总结并比较了对数似然比量度下置信传播算法的四种改进算法和三种消息迭代模式。4.提出了准循环低密度校验码的两种部分并行译码结构,选择其中译码速度较快的一种在ALTERA公司的StratixII-EP2S90F1020C5 FPGA器件实现了DTMB系统中三种准循环低密度校验码的译码器。更多还原

【Abstract】 The design and implementation of the encoder and decoder for Low-Density Parity-Check (LDPC) codes on FPGA device is studied by theoretical analysis and simulation. The main results and contents are as follows.1. The definition and structure of Quasi-Cyclic (QC) LDPC codes are introduced, the characteristics of the QC-LDPC codes in DTMB system are concluded.2. The linear time encoding problem for LDPC codes specified by parity-check matrix is studied. The issue of efficient encoding of QC-LDPC codes using simple shift registers is addressed. Based on this, the implementation design for encoder of QC-LDPC codes in DTMB system is proposed.3. The belief-propagation (BP) decoding algorithm for LDPC codes is presented. Four BP-based decoding algorithms and three kinds of information passing mode are summarized and compared systematically.4. Two partially-parallel decoder architectures for QC-LDPC codes are proposed. Based on the more efficient one a decoder for the three kinds of QC-LDPC codes in DTMB system is implemented on the FPGA device ALTERA StratixII-EP2S90F1020C5.更多还原