【作者】 赵娟；

【导师】 李振坤；

【作者基本信息】 广东工业大学 ， 计算机应用技术， 2008， 硕士

【摘要】 随着自动化控制芯片的应用领域越来越广,功能越来越强大,其设计的复杂度和对其性能的要求也就越来越高。控制芯片关键的部件是接口和终端,因此,人们对控制接口和终端的设计进行了深入的研究和实践,并不断地取得进步。而算术部件不作为控制芯片的主要组成部分,人们对其的研究也就相对少的多,当前大部分控制芯片中使用的是传统的算术部件,其性能远远落后于接口的性能。传统算术部件的设计方法,在资源有限的情况下,不是存在速度问题,就是存在面积和功耗问题:面积和功耗较低的简单设计,由于采用了串行思想来循环计算的,因此,速度比较慢;而传统的性能稍高的算术部件设计方法,面积较大,功耗也相对较高,其设计比较复杂,硬件实现比较难困难。基于现场可编程门阵列(Field-Programmable Gate Array,简称FPGA)算术部件的设计可以根据控制芯片的实时要求,对控制芯片中使用的现有FPGA算术部件进行改进,在占用资源少量增加的基础上,获得速度上的提高。最终通过提高基于FPGA的算术部件的性能,提高整个控制芯片甚至控制系统的性能。首先,对基于FPGA的加法器的改进工作:结合了当前性能较优的进位选择算法和超前进位算法的优缺点,通过将计算数据进行分组,采用组内超前计算,组间进位选择的方案对传统超前进位加法器进行改进,并且组内还使用了流水线技术,来进一步提高加法器的计算速度。其次,对基于FPGA的乘法器的改进工作:求部分积算法上,采用了改进Booth算法,来减少部分积的数目;在部分积的压缩上,使用了5-2压缩器对传统的4-2压缩树结构进行了改进。再次,对基于FPGA的除法器的改进设计:设计实现了32位Radix-16 SRT除法器,在该除法器中,因每次循环都会得到4位商位,减少了商位计算的循环次数。另外,在VerilogHDL编码实现时预先计算出奇数倍的除数,而不是现用现计算,减少计算过程中的冗余。最后,浮点部件的设计,主要对基于FPGA的浮点加法器进行了研究和改进:实现双通道除法器结构中的前导1预测电路(LOP)与定点加法器并行执行;对尾数的移位实现上,实现了快速移位寄存器,并且其中的定点加法器使用了本文设计的改进超前进位加法器。本文的创新之处:针对FPGA丰富的硬件资源以及VerilogHDL硬件描述语言编程实现的简易性,设计实现了高性能的基于FPGA的算术部件。主要是对应用于控制芯片中的基于FPGA的传统算术部件的设计算法和电路结构的改进,提高了加法、乘法和除法以及浮点加法算术部件的性能,在一定程度上提高了控制芯片的性能。更多还原

【Abstract】 With the applications of automatic unit controller chip more widely, and its function are more and more mightiness, the complexity of design is increasing, its performance requirements are also getting higher and higher. The key components of controller chip are interface and terminals, and their performances are determined the level of the entire controller system’s performance directly, therefore, people in-depth study the interface and terminals for the design of controller chips and continue to make progress. However arithmetic unit as part of controller chips, its performance also can infect performance of the entire controller system.The performance of most current arithmetic unit used in controller chip is lagging far behind the performance of interface.The design of traditional arithmetics not only have speed defect, but also have problem in area and power.The simple design of arithmetic unit which has smaller area and power due to the serial thinking of the cycle of calculation,so it has slower speed. The special design of high-performance arithmetic has larger area, and high power consumption with low performance, whose structure is more complicated, more difficult to implement with hardware.Based on FPGA arithmetic unit which is parts of the controller chip is designd under the control of real-time requirements, due to increase in size, on the basis of the controller chips used in the existing FPGA arithmetic unit to increase speed.And by improving performance of arithmetic unit to improve the performance of the controller chip or even controller system.First, the adder improvements: Through divising the calculation data, with the advantages and disadvantages of the current optimum performance carry-select algorithm and carry-lookahead algorithm and using the group ahead, the group binary options to improve the design method of traditional CLA. And the group also used the assembly line technology, to further enhance the computing speed adder.Second, the improving work of multiplier: for the algorithms of part-product, using the improved Booth algorithm to reduce the number of part-product.And in order to reduce redundancy in the calculate process using 5-2 compression to improve the traditional 4-2 compressed tree structure.Third, the improved design of division: designed and implemented the 32-bit Radix-16 SRT division. The divider as a result of each cycle will be four to place, to reduce the frequency of the cycle-bit computing. In addition, VerilogHDL coding surprisingly several times when calculated in advance the divisor, which is not used is calculated to reduce redundancy in the process of calculation.Finally, the design of the floating-point parts, mainly on the floating-point adder have been studied and improved: to achieve dual-channel structure of the division leader a prediction circuit (LOP) and fixed-point adder parallel implementation of the displacement of Mantissa achieve, To achieve a rapid shift register, and using improved CLA which was designed in this paper as one sentinel adder which used in this circuit structure.In this paper, the innovation: With the FPGA hardware design as well as the advantages of the achieve simplicity with VerilogHDL hardware description language programming designed the high-performace Basic-FPGA arithmetic unit. Mainly improved circuit structure and implement algorithms of traditional FPGA-based arithmetic unit in the most of controller chips to improve the performace of FPGA-based addition, multiplication and division and floating-point adder. To a certain extent improved the performance of the controller chip.更多还原