【作者】 项傅佳；

【导师】 吴丽华；

【作者基本信息】 哈尔滨理工大学 ， 检测技术与自动化装置， 2007， 硕士

【摘要】 集成电路被称为IC,是在硅板上集合多种电子元器件实现某种特定功能的电路模块,它是电子设备中最重要的部分,承担着运算和存储的功能。集成电路的应用范围覆盖了军工、民用几乎所有的电子设备,可以说集成电路是计算机业、数字家电业、通信等行业的“心脏”。随着微电子技术的发展,集成电路的规模越来越大,结构越来越复杂,传统的测试生成算法已不能满足要求,因此集成电路测试研究的重点主要集中在研究新的更加有效的测试生成算法和电路的可测性设计技术上。本论文主要研究数字集成电路的多故障测试生成算法及可测性设计技术,以提高算法的故障覆盖率、减少测试生成时间及减少测试矢量的产生和施加为研究目标,重点研究了以下内容:研究了基于布尔差分的组合电路测试生成算法,针对布尔差分算法需要进行大量的异或运算,提出了可不用异或运算,而是通过求解恒等式及约束条件来得到完全测试集的方法,此方法避免了大量的布尔差分运算。研究了多固定型故障的测试生成算法,该方法是将多固定型故障转化为单固定型故障来处理的。当目标故障数为n时,至多需插入n+3个门就可以将此多固定型故障转化为单固定型故障。转换前后的电路在功能上是等价,故障状态也是等价的。研究了基于结构的组合电路多故障测试生成算法——因果函数分析法,该方法主要面向电路的结构,一次性的计算即可找到检测全部电路的测试矢量。研究了九值算法及其改进算法在时序电路中的应用,它比一般的D算法在作D驱赶时要减少很多次无用的计算,此算法充分考虑了故障在重复阵列模型中的重复影响作用,大大减少了计算的工作量。研究了基于Reed-Muller模式的组合电路的可测性设计方法,该方法采用通用型测试集对电路结构或模块进行设计,用此种方法设计的电路不但可以方便的检测出单固定型故障,而且可以确定故障的具体位置,对于双固定型故障以及多固定型故障也可用此方法检测出来。针对症候群测试不需要产生测试矢量的情况,对电路的症候群测试进行了深入研究。传统的症候群可测性判定条件需要写出电路的逻辑表达式,对于大规模集成电路,按照传统的方式很难进行判断。本文推导出了一元症候群和二元症候群可测性判定条件的新形式,并由此推出了多元症候群的判定条件。利用该判定条件,既可直接进行多元症候群判定,不必写出电路的逻辑表达式,又可保证症候群可测。更多还原

【Abstract】 Intergrated Circuits are called IC, and they are the module of circuits which are used to accomplish some function by intergrating a lot of elements in Silicon Board. They are the most important parts in electron devices, and they undertake calculating and memory. We can say that IC are the heart for the business of computer, digital family electronic and communication and so on. IC cover almost all electron devices for military projects and civil use. With the development of microelectronic, the scales of IC become larger and larger and the structures of IC become more and more complicated. The traditional test generation algorithms can’t meet demand, so the key points of testing research for integrated circuits focus on the research of new and effective test generation algorithms and design for testability.In this dissertation, the multi-fault test generation algorithms and design for testability for intergrated circuits has been studied for the purpose of improving faults coverage, reducing the test generation time, and reducing generation and applications of test patterns. The main contents are as follows:The test generation algorithms based on Boolean difference for combina- tionnal circuits has been studied. Considering that there are a lot of exclusive OR operations in the Boolean difference, we proposed a simplified method, and test patterns can be obtained only by solving the identity and constraint conditions without exclusive OR, it avaids a lot of calculations by this method.A test generation algorithm in combinational circuits has been studied to equalize any given multiple stuck-at faults as a single stuck-at fault. The procedure requires insertion of at most n+3 gates, when the multiplicity of the targeted fault is n. We prove that the modeled circuit is functionally equivalent to the original circuit and the targeted multi-fault is equivalent to the single stuck-at fault.The causal analysis algorithm which bases on structure is multi-fault test generation algorithm for combinational circuits, and all the test patterns can be found by one operation in the algorithm.The application of the 9-value algorithm and the improved algorithm in sequential circuits have been studied. A lot of frivolous operation used D-driver in D-algorithm are reduced in 9-value algorithm and the double affects are considered in repeated array so the computational efforts reduce.Design for testability based on Reed-Muller for combinational circuits has been studied. In consideration of the problem that test patterns generation of combinational circuits needs much resource, we have made a research on the combinational circuits based on Reed-Muller. The circuit structure or module designed in this way may be tested by general test patterns set. It can not only detect single-fault easily, but also define the fault location. Besides the double-fault and multi-fault can also be detected by this method.Since generating test patterns are not needed in the course of Syndrome testing, Syndrome of circuits has been thoroughly studied. As the logical expression is needed to be given for the traditional Syndrome test, it is difficult to test for the VLSI. In this dissertation, first order and second order Syndrome testable new conditions have been derived, and the high-order test Syndrome testable condition can be obtained therefrom. By making use of it, we can fulfill the judgment of high-order Syndrome directly with no need of giving the logical expression. In addition, it can be ensured that Syndrome of circuits would be testable.更多还原