【作者】 孙家讹；

【导师】 陈军宁； 柯导明；

【作者基本信息】 安徽大学 ， 电路与系统， 2007， 硕士

【摘要】 集成电路对于高速、高集成度、大信息存储量的追求使得MOS器件的尺寸持续缩小，但是随着MOS器件尺寸的缩小，许多原本在长沟MOS器件中不重要的参数在小尺寸器件中变得显著，并影响器件的性能。因此，有很多的研究报告都在讨论如何使得MOS器件在尺寸缩小的情况下，依然保持长沟道器件的良好特性。在小尺寸MOSFET中，为了减小短沟道效应，采取了增加沟道掺杂和减小栅氧化层厚度等措施。高的掺杂浓度和强的电场使得量子效应对器件的性能影响不可忽视。长期以来，反型层和积累层中的量子效应对MOS器件性能的影响被广泛关注。近期，多晶硅中量子效应对器件性能的影响也被研究。此外，由于源漏延伸(SDE)结构能有效地抑制热载流子效应和短沟道效应，它已成为小尺寸CMOS的标准工艺技术。但是，源漏延伸结构会引起寄生电阻的增加，并且，由于寄生电阻不能随着MOS器件的缩小而缩小，这使得寄生电阻在总的电阻中占有很大的比例，严重影响器件的输出特性和频率特性。本文首先介绍了MOS器件尺寸缩小的趋势，面临的工艺技术和器件物理效应上的挑战，介绍了MOS器件结构、材料和工艺的发展趋势。在对器件量子效应的分析建模上，作者首先对反型层中量子效应进行了分析。基于三角势场近似，通过求解薛定谔方程，得到了载流子的分立能级和对应的波函数，给出了反型层中载流子的分布。从反型层载流子分布出发，建立了表面电容和对应阈值时的表面势解析表达式，分析了反型层量子效应对MOS阈值电压和有效栅电容的影响；接着作者利用数值模拟的结果和曲线拟合，对多晶硅中量子效应进行了解析建模，得到了多晶硅栅中的载流子分布和电压降，研究了多晶硅量子效应对MOS器件阈值电压的影响，定量分析了栅电极电容对有效栅电容的影响。由于寄生电阻不能随着MOS器件的缩小而缩小，使得寄生电阻对MOS器件性能的影响不可忽视，为了准确地预测源漏极寄生电阻，分析器件参数对寄生电阻的影响，一个有效的MOS器件寄生电阻模型对于MOS器件的设计是十分必要的。在寄生电阻的分析中，作者先介绍了长沟道寄生电阻模型和短沟道寄生电阻模型，分析了短沟道MOS寄生电阻模型在栅压较低时存在较大误差的原因。分析认为，误差的原因在计算积累层电荷上。短沟道寄生电阻模型在计算时假设积累层厚度为零，从而得到积累层电荷计算公式，这在栅压小的时候存在较大的误差。根据分析结果，不再假设积累层厚度为零，给出了新的积累层电荷计算方程，对短沟道寄生电阻模型进行了改进，改进的模型经过数值模拟验证，确实能更好的预测MOS器件的寄生电阻。最后作者模拟分析了器件结构参数对源漏寄生电阻的影响，以期能对器件的设计进行指导，提高器件的性能。更多还原

【Abstract】 The pursue of high speed, high integration and large memory of information make the size of MOSFET scale down continuously, which results in this fact that some parameters who can be ignored in long-channel devices become more aggressively in short channel MOSFETs and then affect performances of the device. Therefore, many studies talked about how to maintain performances of long channel MOSFETs when the size of MOSFETs reduced. To reduce the short-channel effects, the measures like increasing channel doping concentration and reducing gate-oxide thickness is proposed. Then quantum effects on the devices performances should be considered due to the high doping concentration and the strong electric field. For a long time, the quantum effects in the accumulation and inversion layer are of significant concern. Nowadays, the infection of quantum effects of polycrystalline silicon is also investigated. Furthermore, the SDE(Source Drain Extension) structure has became the standard CMOS process which can restrain the hot carrier effects and short-channel effects effectively. Unfortunately, SDE would lead to the increase of parasitic resistances. Meanwhile, as the parasitic resistance cannot be reduced following the scaling down of MOSFETs, it causes the parasitic resistance accounting for a large proportion in the total resistance, and then the output characteristics and frequency characteristics are reduced.In this paper, the scaling down trend of MOSFETs and the great challenges for the process and physical mechanisms are introduced. And then the developments of MOSFETs structure, material and the process are discussed.To model the quantum effects in short channel MOSFETs, the quantum effects in the inversion layers is analyzed at first. Based on the approximation of triangular potential well, the schrodinger equation is solved and electron eigen energies and eigen wave functions can be obtained, then the carriers distribution in the inversion layers is given. According to this distribution, the expressions of surface capacitance and surface potential corresponding threshold voltage are presented. Then the influence of quantum effects in the inversion layers on the MOSFET threshold voltage and effective gate-capacitance are analyzed. Subsequently, analytical model of the quantum effects in polycrystalline silicon is presented, obtaining the carrier distribution and voltage drop in polycrystalline silicon. Through numerical simulation and figure fitting, the influence of quantum effects in polycrystalline silicon on MOSFETs threshold voltage and the influence of gate electrode capacitance on the effective gate-capacitance are researched.As the parasitic resistance cannot be reduced with the scaling down of MOSFETs, the influence of parasitic resistance on the MOSFETs performance shouldn’t be neglected. To predict the parasitic resistance of the drain and source electrode precisely and analyze the relationship between the structure parameters and parasitic resistance, it is necessary to establish an effective parasitic resistance model. While analyzing the parasitic resistance, the parasitic resistance model of the long-channel and short-channel MOSFETs are introduced respectively, and the reason why the parasitic resistance model of short-channel MOSFETs exists great error is proposed when the Vg is lower. The reason can be ascribe to the calculation of the charge of accumulation layer. In the parasitic resistance model of short channel MOSFETs, the thickness of accumulation layer is assumed to zero, but the error is large at the low Vg. According to the results of analysis, the thickness of the accumulation layer cannot be assumed to zero and a new equation to solve the charge of the accumulation layer is given. The results show good accordance with actual parasitic resistance. At the end, the influences of device structure parameters on parasitic resistance are simulated and analyzed, which can be used in practical device design and improve device performances.更多还原