【作者】 陈畅；

【导师】 陆生礼；

【作者基本信息】 东南大学 ， 微电子学与固体电子学， 2005， 硕士

【摘要】 近年来等离子显示器(PDP)已成为高清晰度电视(HDTV)及壁挂式彩电的主流产品之一。然而过高的成本成为PDP普及的主要障碍,其中昂贵的驱动芯片是PDP高成本的一个重要方面,因此,迫切需要研制出具有自主知识产权的低成本的PDP驱动芯片。本课题任务就是针对基于体硅工艺的PDP高压驱动芯片的开发,研制出高性能的高低压转换电路,以满足低成本PDP驱动芯片的市场需求。本论文综述了PDP的特点、应用以及国内外PDP行列高压驱动芯片的研究和发展现状。对PDP驱动芯片中高低压转换电路的研究和发展现状做了简略的介绍,分析了这类电路的特点和改进方向。以此为基础提出了一系列用于指导该类电路开发的设计原则和一套科学可行的设计方案。随后在这些原则的指导下,应用该方案基于无锡上华1.5μm标准CMOS工艺线设计了PDP数据选址芯片SED9006S7中的高低压转换电路。该设计方案分低压延时驱动电路设计和信号电平提升电路设计两部分,低压延时驱动部分又分为延时级电路设计和驱动级电路设计。在研究了多种延时级电路的基础上提出了一种易于调整延迟时间的新结构的延时级电路。在信号电平提升电路的设计优化方案中,针对最常用的CMOS六管结构的高压电路通过Hspice软件仿真确定了各设计参数对最终设计目标的影响。该设计方案分为三个步骤,逐步缩小了优化范围,最终通过高低压电路的整体联调确定了应用在PDP的数据选址芯片SED9006S7中的高低压转换电路的各器件尺寸参数。在对版图进行了工艺兼容性设计和工艺可靠性设计之后在无锡上华流片。对流片后的测试结果进行了分析和比较,验证了该设计的正确性和可行性。在论文最后的展望中提出了该课题的后续研究方向。SED9006S7芯片的实测结果显示该芯片的电压、电流、功耗和频率等技术指标均符合实用要求,且优于国外同类芯片,而加工成本也大大低于国外同类产品。该设计方案的提出,向研制具有自主知识产权的低成本的PDP驱动芯片的目标又迈出了坚实的一步。本论文在低压电路结构上有所创新,提出了一种易于调节低压驱动信号延时大小的低压延时电路。同时对常用的实用型的信号电平提升电路的设计方法进行了摸索和总结,归纳出一套完整可行的设计验证方案。目前国内对PDP驱动芯片中的高低压转换的电路的研究还比较薄弱,在这个方面的文献和资料都比较少,本论文的研究具有一定的开拓性,希望可以抛砖引玉,为后续的研究工作提供一个有价值的参考和启发。更多还原

【Abstract】 In recent years, PDP (Plasma Display Panel) was regard as one of the first choices of HDTV (High Fidelity TV) and the on-wall-TV. In the authority’s prediction report, PDP technology will remain the main stream position of the market in future 10 years. But the much high price makes it hard to be afforded by Chinese consumers. To lower the high price of PDP, we must lower the price of PDP driver chips. So we have to make PDP driver ICs’design more easily more reliably and more cheaply.In this dissertation, a whole scheme was presented to design the LV-to-HV interface circuit that plays a key part of PDP driver ICs. This scheme will guide and help designers to design PDP driver ICs more conveniently. At the beginning of the dissertation, the characteristics and the development of PDP driver ICs are introduced. And then the same to the LV (low voltage)-to-HV (high voltage) interface circuit is done. According to the introduction, several design principles are concluded. With the help of these principles, a scientific and executable scheme to design the LV-to-HV interface circuits is proponed. For easier to understand how this scheme works, a PDP data addressing IC -SED9006S7- is taken as an instance to illustrate the design flow. The design scheme includes LV (low voltage) part and HV (high voltage) part. In the LV part a novel structure for LV time delay circuit is proposed beside the design method discussed for time delay circuit and drive capability circuit. And in the HV part a 3-step design approach is proposed to make LV-to-HV level shifter work more reliably and cost less power. After the layout design was completed the chip was tape out.The real test result of the IC designed by this theme indicated that all HV parameters were met the need of practicality and their characteristics were better than the same type PDP driver IC designed by foreign companies. All this proved the validity and superiority of the design scheme propose in this dissertation. At last, a durative research direction was brought forward in summary.更多还原