【作者】 邵晶波；

【导师】 马光胜；

【作者基本信息】 哈尔滨工程大学 ， 计算机应用技术， 2007， 硕士

【摘要】 随着芯片设计向深亚微米工艺的推进，数字IC的设计技术水平越来越高，特征尺寸越来越小，集成密度越来越大。IC制造能力的不断攀升对IC测试提出了更大的挑战。为了保证高质量的IC产品，我们要在产品制造之前对其进行测试，因为它是保证IC成品率的一个重要途径。已提出的各种设计方法使得测试数据量极其庞大，而现有的测试设备的速度、存储容量和I／O通道的处理能力满足不了测试需求，从而成为限制高质量测试的瓶颈。因此研究新型有效的数字集成电路测试生成、测试压缩算法具有十分重要的理论价值和实际意义。本文总结了近年来时延测试领域的研究成果，重点分析了测试数据压缩技术，讨论了各种方法的优缺点。IC制造工艺向深亚微米的推进带来许多新问题，如串扰问题、定时问题等等，针对解决这些问题的新测试方法又大大提高了测试成本。近几年为了降低测试成本，提高测试效率，提出了各种各样的测试压缩算法，这些算法可以很好的提高测试压缩效率，这些方法大都需要额外的硬件电路。本文给出了一种基于扫描链隐藏技术和X-压缩的多扫描电路的测试压缩方法—全方位的测试压缩方法。该方法采用可变宽度的扫描链解压缩方法对测试输入进行解压缩，并且测试响应结合了X-压缩的优点，测试响应整合器最小化故障被屏蔽的概率，扫描链的结构采取广播扫描模式，在此基础上对其改进使其可同时处理取值相反的触发器。并行模式可处理取值相同的测试向量以及与已有的测试向量的对应位互为反值的测试向量。串行模式可进一步处理剩余的紧凑的测试向量值，由于并行部分采用反相器可实现触发器复用，从而降低了硬件开销。本文的测试压缩算法的优点是：可节省测试设备的存储需求，减少测试输入输出引脚数和测试通道数，降低测试应用时间，从而全面提高测试激励数据和测试响应数据的压缩率。实验结果证明了该算法的以上优势。文章还研究了全方位的测试压缩方法在系统芯片上应用，并讨论了如何实现这种IP核测试压缩方法。更多还原

【Abstract】 With chip designs advancing to VDSM (Very Deep Submicron) era, the design level of digital IC is becoming increasingly higher with shrinking feature sizes and more and larger density. To obtain high quality IC products, it is required to perform IC test for the products before manufacturing them, because it is one of the important ways to guarantee the quality of the finished product. While the ever-enhancing IC manufacturing abilities pose great challenges to IC test. While the current ATE fails the requirement because of its restricted storage, available pins and unbearable test application time. The previously proposed designs mostly require huge test data volume, forming a bottleneck that restricts high quality test. Test compression has been a heated research topic in recent years. Therefore it is significant for us to explore novel, effective test generation and test compression methods.This paper overviews the recent research work on delay testing, focusing fault set compaction and test data compression for scan designs, and approaches to delay testing are analyzed, pros and cons of each method is discussed. With the enhancement of IC manufacturing abilities, many new issues such as crosstalk, timing etc arise. Among them lots of novel test approaches to solve these problems require high test costs. Lately, various methods have been proposed to deal with the problems of ever-increasing test costs and test efficiency. The achieved good results prove the effectiveness of the previously presented algorithms; however they are mostly at the cost of extra hardware overhead. To alleviate the problems, we put forward a drastic test data scheme based on scan chain concealment and X-compact techniques for multiple scan designs. Adjustable width scan chain strategy is employed for test stimuli decompression, and test response takes the advantages of X-compact. A response shaper further minimizes the probability of fault masking. The enhanced broadcast-scan based mode for CUT (circuit under test) is able to deal with FFs (flip-fops) with the opposing values as well as the identical values. Two modes can handle the rest compact FF values after filling the unknown values: Under parallel mode, test vectors with the same corresponding bit values can be processed concurrently. And if there are such test vectors which have the corresponding opposite bit values as the existing test vectors, we also put them in parallel part. The second mode-serial mode deals with the rest compact test vectors. Due to the usage of inverter in parallel part, hardware overhead is decreased.The merits of proposed approach are as follows. Test storage requirement is reduced drastically, and test input/output pins, test channels coupled with test application time decrease, thus improving test compression ratio completely. The experimental results on benchmark circuits ISCAS’89 demonstrate the advantages mentioned above.SoC (System-on-Chip) has been one of the hot research topics with the rapid development of science and technology. As for IP core test compression, we also explored how to introduce the above mentioned method (drastic test compression) into this system harmoniously. And implementation of the idea is also given in this paper.更多还原